668 lines
28 KiB
Python
Executable File
668 lines
28 KiB
Python
Executable File
#!/usr/bin/env python
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import argparse
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from operator import itemgetter
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from migen import *
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from migen.build.generic_platform import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import kasli_soc
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from misoc.interconnect.csr import *
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from misoc.cores import virtual_leds
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from artiq.coredevice import jsondesc
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from artiq.gateware import rtio, eem_7series
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.drtio.transceiver import gtx_7series, eem_serdes
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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import dma
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import analyzer
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import acpki
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import drtio_aux_controller
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import zynq_clocking
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import wrpll
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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eem_iostandard_dict = {
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0: "LVDS_25",
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1: "LVDS_25",
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2: "LVDS",
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3: "LVDS",
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4: "LVDS",
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5: "LVDS",
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6: "LVDS",
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7: "LVDS",
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8: "LVDS_25",
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9: "LVDS_25",
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10: "LVDS",
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11: "LVDS",
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}
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def eem_iostandard(eem):
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return IOStandard(eem_iostandard_dict[eem])
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class SMAClkinForward(Module):
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def __init__(self, platform):
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sma_clkin = platform.request("sma_clkin")
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sma_clkin_se = Signal()
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cdr_clk_se = Signal()
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cdr_clk = platform.request("cdr_clk")
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self.specials += [
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Instance("IBUFDS", i_I=sma_clkin.p, i_IB=sma_clkin.n, o_O=sma_clkin_se),
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Instance("ODDR", i_C=sma_clkin_se, i_CE=1, i_D1=1, i_D2=0, o_Q=cdr_clk_se),
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Instance("OBUFDS", i_I=cdr_clk_se, o_O=cdr_clk.p, o_OB=cdr_clk.n)
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]
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class GTPBootstrapClock(Module):
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def __init__(self, platform, freq=125e6):
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self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
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self.cd_bootstrap.clk.attr.add("keep")
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bootstrap_125 = platform.request("clk125_gtp")
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bootstrap_se = Signal()
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clk_out = Signal()
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platform.add_period_constraint(bootstrap_125.p, 8.0)
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self.specials += [
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Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=bootstrap_125.p, i_IB=bootstrap_125.n,
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o_O=bootstrap_se,
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p_CLKCM_CFG="TRUE",
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p_CLKRCV_TRST="TRUE",
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p_CLKSWING_CFG=3),
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Instance("BUFG", i_I=bootstrap_se, o_O=clk_out)
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]
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if freq == 125e6:
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self.comb += self.cd_bootstrap.clk.eq(clk_out)
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elif freq == 100e6:
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pll_fb = Signal()
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pll_out = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_CLKIN1_PERIOD=8.0,
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i_CLKIN1=clk_out,
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i_CLKFBIN=pll_fb,
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o_CLKFBOUT=pll_fb,
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# VCO @ 1GHz
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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# 100MHz for bootstrap
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p_CLKOUT1_DIVIDE=10, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_out,
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),
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Instance("BUFG", i_I=pll_out, o_O=self.cd_bootstrap.clk)
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]
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else:
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raise ValueError("Bootstrap frequency must be 100 or 125MHz")
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class GenericStandalone(SoCCore):
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def __init__(self, description, acpki=False):
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self.acpki = acpki
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clk_freq = description["rtio_frequency"]
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with_wrpll = description["enable_wrpll"]
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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ident = description["variant"]
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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self.config["HW_REV"] = description["hw_rev"]
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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clk_synth_se_buf = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se
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),
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Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_se_buf),
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]
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fix_serdes_timing_path(platform)
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se_buf)
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platform.add_false_path_constraints(
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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self.csr_devices.append("sys_crg")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.crg.cd_sys = self.sys_crg.cd_sys
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if with_wrpll:
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self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
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self.submodules.wrpll = wrpll.WRPLL(
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platform=self.platform,
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cd_ref=self.wrpll_refclk.cd_ref,
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main_clk_se=clk_synth_se)
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self.csr_devices.append("wrpll_refclk")
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self.csr_devices.append("wrpll")
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self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
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self.config["HAS_SI549"] = None
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self.config["WRPLL_REF_CLK"] = "SMA_CLKIN"
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else:
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self.submodules += SMAClkinForward(self.platform)
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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self.grabber_csr_group = []
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eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
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for i in (0, 1):
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print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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user_led = self.platform.request("user_led", i)
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phy = ttl_simple.Output(user_led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(
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self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"]
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)
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.config["KI_IMPL"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.csr_devices.append("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.ps7.s_axi_hp1)
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self.csr_devices.append("rtio_analyzer")
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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self.sys_crg.cd_sys.clk, getattr(self, grabber).deserializer.cd_cl.clk)
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class GenericMaster(SoCCore):
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def __init__(self, description, acpki=False):
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clk_freq = description["rtio_frequency"]
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with_wrpll = description["enable_wrpll"]
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has_drtio_over_eem = any(peripheral["type"] == "shuttler" for peripheral in description["peripherals"])
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self.acpki = acpki
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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ident = description["variant"]
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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self.config["HW_REV"] = description["hw_rev"]
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.gt_drtio = gtx_7series.GTX(
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clock_pads=platform.request("clk_gtp"),
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pads=data_pads,
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clk_freq=clk_freq)
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self.csr_devices.append("gt_drtio")
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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txout_buf = Signal()
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gtx0 = self.gt_drtio.gtxs[0]
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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ext_async_rst = Signal()
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(
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self.platform,
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self.ps7,
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txout_buf,
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clk_sw=self.gt_drtio.stable_clkin.storage,
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clk_sw_status=gtx0.tx_init.done,
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ext_async_rst=ext_async_rst)
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self.csr_devices.append("sys_crg")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.crg.cd_sys = self.sys_crg.cd_sys
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platform.add_false_path_constraints(
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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fix_serdes_timing_path(platform)
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self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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if with_wrpll:
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
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self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
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self.submodules.wrpll = wrpll.WRPLL(
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platform=self.platform,
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cd_ref=self.wrpll_refclk.cd_ref,
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main_clk_se=clk_synth_se)
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self.csr_devices.append("wrpll_refclk")
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self.csr_devices.append("wrpll")
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self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
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self.config["HAS_SI549"] = None
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self.config["WRPLL_REF_CLK"] = "SMA_CLKIN"
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else:
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self.submodules += SMAClkinForward(self.platform)
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_drtio_over_eem:
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self.eem_drtio_channels = []
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if has_grabber:
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self.grabber_csr_group = []
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eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
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for i in (0, 1):
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print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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user_led = self.platform.request("user_led", i)
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phy = ttl_simple.Output(user_led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
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self.drtio_csr_group = []
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self.drtioaux_csr_group = []
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self.drtioaux_memory_group = []
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self.drtio_cri = []
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for i in range(len(self.gt_drtio.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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self.drtio_csr_group.append(core_name)
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self.drtioaux_csr_group.append(coreaux_name)
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self.drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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core = cdr(DRTIOMaster(self.rtio_tsc, self.gt_drtio.channels[i]))
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setattr(self.submodules, core_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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size = coreaux.get_mem_size()
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memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
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self.axi2csr.register_port(coreaux.get_rx_port(), size)
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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if has_drtio_over_eem:
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self.add_eem_drtio(self.eem_drtio_channels)
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self.add_drtio_cpuif_groups()
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self.submodules.rtio_core = rtio.Core(
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self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"]
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)
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.config["KI_IMPL"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri] + self.drtio_cri,
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enable_routing=True)
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self.csr_devices.append("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.ps7.s_axi_hp1)
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self.csr_devices.append("rtio_analyzer")
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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self.submodules.virtual_leds = virtual_leds.VirtualLeds()
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self.csr_devices.append("virtual_leds")
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self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
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for i, channel in enumerate(self.gt_drtio.channels)]
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def add_eem_drtio(self, eem_drtio_channels):
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# Must be called before invoking add_rtio() to construct the CRI
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# interconnect properly
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self.submodules.eem_transceiver = eem_serdes.EEMSerdes(self.platform, eem_drtio_channels)
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self.csr_devices.append("eem_transceiver")
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self.config["HAS_DRTIO_EEM"] = None
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self.config["EEM_DRTIO_COUNT"] = len(eem_drtio_channels)
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cdr = ClockDomainsRenamer({"rtio_rx": "sys"})
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for i in range(len(self.eem_transceiver.channels)):
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channel = i + len(self.gt_drtio.channels)
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core_name = "drtio" + str(channel)
|
|
coreaux_name = "drtioaux" + str(channel)
|
|
memory_name = "drtioaux" + str(channel) + "_mem"
|
|
self.drtio_csr_group.append(core_name)
|
|
self.drtioaux_csr_group.append(coreaux_name)
|
|
self.drtioaux_memory_group.append(memory_name)
|
|
|
|
core = cdr(DRTIOMaster(self.rtio_tsc, self.eem_transceiver.channels[i]))
|
|
setattr(self.submodules, core_name, core)
|
|
self.drtio_cri.append(core.cri)
|
|
self.csr_devices.append(core_name)
|
|
|
|
coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
|
|
setattr(self.submodules, coreaux_name, coreaux)
|
|
self.csr_devices.append(coreaux_name)
|
|
|
|
size = coreaux.get_mem_size()
|
|
memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
|
|
self.axi2csr.register_port(coreaux.get_rx_port(), size)
|
|
self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
|
|
|
|
def add_drtio_cpuif_groups(self):
|
|
self.add_csr_group("drtio", self.drtio_csr_group)
|
|
self.add_csr_group("drtioaux", self.drtioaux_csr_group)
|
|
self.add_memory_group("drtioaux_mem", self.drtioaux_memory_group)
|
|
|
|
|
|
class GenericSatellite(SoCCore):
|
|
def __init__(self, description, acpki=False):
|
|
clk_freq = description["rtio_frequency"]
|
|
with_wrpll = description["enable_wrpll"]
|
|
|
|
self.acpki = acpki
|
|
|
|
platform = kasli_soc.Platform()
|
|
platform.toolchain.bitstream_commands.extend([
|
|
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
|
|
])
|
|
ident = description["variant"]
|
|
if self.acpki:
|
|
ident = "acpki_" + ident
|
|
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
|
|
|
|
self.config["HW_REV"] = description["hw_rev"]
|
|
|
|
data_pads = [platform.request("sfp", i) for i in range(4)]
|
|
|
|
self.submodules.gt_drtio = gtx_7series.GTX(
|
|
clock_pads=platform.request("clk_gtp"),
|
|
pads=data_pads,
|
|
clk_freq=clk_freq)
|
|
self.csr_devices.append("gt_drtio")
|
|
|
|
txout_buf = Signal()
|
|
gtx0 = self.gt_drtio.gtxs[0]
|
|
self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
|
|
|
|
ext_async_rst = Signal()
|
|
|
|
self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
|
|
self.submodules.sys_crg = zynq_clocking.SYSCRG(
|
|
self.platform,
|
|
self.ps7,
|
|
txout_buf,
|
|
clk_sw=self.gt_drtio.stable_clkin.storage,
|
|
clk_sw_status=gtx0.tx_init.done,
|
|
ext_async_rst=ext_async_rst)
|
|
platform.add_false_path_constraints(
|
|
self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
|
|
self.csr_devices.append("sys_crg")
|
|
self.crg = self.ps7 # HACK for eem_7series to find the clock
|
|
self.crg.cd_sys = self.sys_crg.cd_sys
|
|
|
|
fix_serdes_timing_path(platform)
|
|
|
|
self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
|
|
self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
|
|
|
|
self.rtio_channels = []
|
|
has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
|
|
if has_grabber:
|
|
self.grabber_csr_group = []
|
|
eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
|
|
for i in (0, 1):
|
|
print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
|
|
user_led = self.platform.request("user_led", i)
|
|
phy = ttl_simple.Output(user_led)
|
|
self.submodules += phy
|
|
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
|
|
self.rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
|
|
|
|
drtioaux_csr_group = []
|
|
drtioaux_memory_group = []
|
|
drtiorep_csr_group = []
|
|
self.drtio_cri = []
|
|
for i in range(len(self.gt_drtio.channels)):
|
|
coreaux_name = "drtioaux" + str(i)
|
|
memory_name = "drtioaux" + str(i) + "_mem"
|
|
drtioaux_csr_group.append(coreaux_name)
|
|
drtioaux_memory_group.append(memory_name)
|
|
|
|
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
|
|
|
|
if i == 0:
|
|
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
|
|
core = cdr(DRTIOSatellite(
|
|
self.rtio_tsc, self.gt_drtio.channels[i],
|
|
self.rx_synchronizer))
|
|
self.submodules.drtiosat = core
|
|
self.csr_devices.append("drtiosat")
|
|
else:
|
|
corerep_name = "drtiorep" + str(i-1)
|
|
drtiorep_csr_group.append(corerep_name)
|
|
|
|
core = cdr(DRTIORepeater(
|
|
self.rtio_tsc, self.gt_drtio.channels[i]))
|
|
setattr(self.submodules, corerep_name, core)
|
|
self.drtio_cri.append(core.cri)
|
|
self.csr_devices.append(corerep_name)
|
|
|
|
coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
|
|
setattr(self.submodules, coreaux_name, coreaux)
|
|
self.csr_devices.append(coreaux_name)
|
|
|
|
mem_size = coreaux.get_mem_size()
|
|
tx_port = coreaux.get_tx_port()
|
|
rx_port = coreaux.get_rx_port()
|
|
memory_address = self.axi2csr.register_port(tx_port, mem_size)
|
|
# rcv in upper half of the memory, thus added second
|
|
self.axi2csr.register_port(rx_port, mem_size)
|
|
# and registered in PS interface
|
|
# manually, because software refers to rx/tx by halves of entire memory block, not names
|
|
self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
|
|
self.config["HAS_DRTIO"] = None
|
|
self.config["HAS_DRTIO_ROUTING"] = None
|
|
self.add_csr_group("drtioaux", drtioaux_csr_group)
|
|
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
|
|
self.add_csr_group("drtiorep", drtiorep_csr_group)
|
|
|
|
if self.acpki:
|
|
self.config["KI_IMPL"] = "acp"
|
|
self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
|
|
bus=self.ps7.s_axi_acp,
|
|
user=self.ps7.s_axi_acp_user,
|
|
evento=self.ps7.event.o)
|
|
self.csr_devices.append("rtio")
|
|
else:
|
|
self.config["KI_IMPL"] = "csr"
|
|
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
|
|
self.csr_devices.append("rtio")
|
|
|
|
self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
|
|
self.csr_devices.append("rtio_dma")
|
|
|
|
self.submodules.local_io = SyncRTIO(
|
|
self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"]
|
|
)
|
|
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
|
|
|
|
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
|
[self.drtiosat.cri, self.rtio_dma.cri, self.rtio.cri],
|
|
[self.local_io.cri] + self.drtio_cri,
|
|
enable_routing=True)
|
|
self.csr_devices.append("cri_con")
|
|
|
|
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
|
|
self.csr_devices.append("routing_table")
|
|
|
|
self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
|
|
self.csr_devices.append("rtio_moninj")
|
|
|
|
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.local_io.cri,
|
|
self.ps7.s_axi_hp1)
|
|
self.csr_devices.append("rtio_analyzer")
|
|
|
|
rtio_clk_period = 1e9/clk_freq
|
|
self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
|
|
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
|
|
|
|
if with_wrpll:
|
|
clk_synth = platform.request("cdr_clk_clean_fabric")
|
|
clk_synth_se = Signal()
|
|
platform.add_period_constraint(clk_synth.p, 8.0)
|
|
self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
|
|
self.submodules.wrpll = wrpll.WRPLL(
|
|
platform=self.platform,
|
|
cd_ref=self.gt_drtio.cd_rtio_rx0,
|
|
main_clk_se=clk_synth_se)
|
|
self.submodules.wrpll_skewtester = wrpll.SkewTester(self.rx_synchronizer)
|
|
self.csr_devices.append("wrpll_skewtester")
|
|
self.csr_devices.append("wrpll")
|
|
self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
|
|
self.config["HAS_SI549"] = None
|
|
self.config["WRPLL_REF_CLK"] = "GT_CDR"
|
|
else:
|
|
self.submodules.siphaser = SiPhaser7Series(
|
|
si5324_clkin=platform.request("cdr_clk"),
|
|
rx_synchronizer=self.rx_synchronizer,
|
|
ultrascale=False,
|
|
rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
|
|
self.csr_devices.append("siphaser")
|
|
self.config["HAS_SI5324"] = None
|
|
self.config["SI5324_SOFT_RESET"] = None
|
|
|
|
gtx0 = self.gt_drtio.gtxs[0]
|
|
platform.add_false_path_constraints(
|
|
gtx0.txoutclk, gtx0.rxoutclk)
|
|
|
|
if has_grabber:
|
|
self.config["HAS_GRABBER"] = None
|
|
self.add_csr_group("grabber", self.grabber_csr_group)
|
|
# no RTIO CRG here
|
|
|
|
self.submodules.virtual_leds = virtual_leds.VirtualLeds()
|
|
self.csr_devices.append("virtual_leds")
|
|
|
|
self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
|
|
for i, channel in enumerate(self.gt_drtio.channels)]
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description="ARTIQ device binary builder for generic Kasli-SoC systems")
|
|
parser.add_argument("-r", default=None,
|
|
help="build Rust interface into the specified file")
|
|
parser.add_argument("-c", default=None,
|
|
help="build Rust compiler configuration into the specified file")
|
|
parser.add_argument("-m", default=None,
|
|
help="build Rust memory interface into the specified file")
|
|
parser.add_argument("-g", default=None,
|
|
help="build gateware into the specified directory")
|
|
parser.add_argument("--acpki", default=False, action="store_true",
|
|
help="enable ACPKI")
|
|
parser.add_argument("description", metavar="DESCRIPTION",
|
|
help="JSON system description file")
|
|
args = parser.parse_args()
|
|
description = jsondesc.load(args.description)
|
|
|
|
if description["target"] != "kasli_soc":
|
|
raise ValueError("Description is for a different target")
|
|
|
|
if description["drtio_role"] == "standalone":
|
|
cls = GenericStandalone
|
|
elif description["drtio_role"] == "master":
|
|
cls = GenericMaster
|
|
elif description["drtio_role"] == "satellite":
|
|
cls = GenericSatellite
|
|
else:
|
|
raise ValueError("Invalid DRTIO role")
|
|
|
|
soc = cls(description, acpki=args.acpki)
|
|
soc.finalize()
|
|
|
|
if args.r is not None:
|
|
write_csr_file(soc, args.r)
|
|
if args.m is not None:
|
|
write_mem_file(soc, args.m)
|
|
if args.c is not None:
|
|
write_rustc_cfg_file(soc, args.c)
|
|
if args.g is not None:
|
|
soc.build(build_dir=args.g)
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|