You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

zynq-7000.cfg 4.7KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211
  1. #
  2. # Xilinx Zynq 7000 SoC
  3. #
  4. # Chris Johns <chrisj@rtems.org>
  5. #
  6. # Setup
  7. # -----
  8. #
  9. # Create a user configuration following the "Configuration Basics" in the user
  10. # documentation. In the file have:
  11. #
  12. # source [find interface/ftdi/flyswatter2.cfg]
  13. # source [find board/zynq-zc706-eval.cfg]
  14. # adapter_khz 2000
  15. # init
  16. #
  17. if { [info exists CHIPNAME] } {
  18. global _CHIPNAME
  19. set _CHIPNAME $CHIPNAME
  20. } else {
  21. global _CHIPNAME
  22. set _CHIPNAME zynq
  23. }
  24. if { [info exists ENDIAN] } {
  25. set _ENDIAN $ENDIAN
  26. } else {
  27. # this defaults to a bigendian
  28. set _ENDIAN little
  29. }
  30. if { [info exists SMP] } {
  31. global _SMP
  32. set _SMP 1
  33. } else {
  34. global _SMP
  35. set _SMP 0
  36. }
  37. #
  38. # PL Tap.
  39. #
  40. # See ug585 ZYNQ-7000 TRM PSS_IDCODE for how this number is constructed.
  41. # 0x03731093 - ZC706 Eval board 1.1
  42. # 0x23731093 - ??
  43. # 0x23727093 - Zedboard Rev. C and D
  44. #
  45. # Set in your configuration file or board specific file.
  46. #
  47. if { [info exists PL_TAPID] } {
  48. set _PL_TAPID $PL_TAPID
  49. } else {
  50. set _PL_TAPID 0x03731093
  51. }
  52. jtag newtap $_CHIPNAME tap -irlen 6 -ircapture 0x001 -irmask 0x003 \
  53. -expected-id $_PL_TAPID
  54. #
  55. # CoreSight Debug Access Port
  56. #
  57. if { [info exists DAP_TAPID] } {
  58. set _DAP_TAPID $DAP_TAPID
  59. } else {
  60. set _DAP_TAPID 0x4ba00477
  61. }
  62. jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x03 \
  63. -expected-id $_DAP_TAPID
  64. #
  65. # GDB target: Cortex-A9, using DAP, configuring only one core
  66. # Base addresses of cores:
  67. # core 0 - 0xF8890000
  68. # core 1 - 0xF8892000
  69. #
  70. # Read from the ROM table with the patch to read the nested table.
  71. #
  72. set _TARGETNAME_0 $_CHIPNAME.cpu.0
  73. set _TARGETNAME_1 $_CHIPNAME.cpu.1
  74. target create $_TARGETNAME_0 cortex_a -coreid 0 \
  75. -endian $_ENDIAN \
  76. -chain-position $_CHIPNAME.dap \
  77. -dbgbase 0x80090000
  78. if { $_SMP } {
  79. echo "Zynq CPU1."
  80. target create $_TARGETNAME_1 cortex_a -coreid 1 \
  81. -endian $_ENDIAN \
  82. -chain-position $_CHIPNAME.dap \
  83. -dbgbase 0x80092000
  84. target smp $_TARGETNAME_0 $_TARGETNAME_1
  85. }
  86. #
  87. # Hack to get the registers into a stable state when first booting a zynq in
  88. # JTAG mode. If r11 is pointing to an invalid address and you use gdb to set a
  89. # register the write will fail because gdb attempts to scan or unwind the
  90. # current frame and the bad address seems to lock the bus up. This code puts
  91. # the registers into the OCM and hopefull safe.
  92. #
  93. proc zynq_clear_registers { target } {
  94. echo "Zynq-7000 Series setup: $target"
  95. set _OCM_END 0x0003FFF0
  96. mww phys 0xF8007000 0x4E00E07F
  97. reg r0 0
  98. reg r1 0
  99. reg r2 0
  100. reg r3 0
  101. reg r4 0
  102. reg r5 0
  103. reg r6 0
  104. reg r7 0
  105. reg r8 0
  106. reg r9 0
  107. reg r10 0
  108. reg r11 $_OCM_END
  109. reg sp_svc $_OCM_END
  110. reg lr_svc $_OCM_END
  111. reg sp_abt $_OCM_END
  112. reg lr_abt $_OCM_END
  113. reg sp_und $_OCM_END
  114. reg lr_und $_OCM_END
  115. }
  116. proc zynq_disable_mmu_and_caches { target } {
  117. # arm mcr pX op1 CRn CRm op2 value
  118. echo "Disable MMU and caches"
  119. # Invalidate caches
  120. catch {
  121. $target arm mcr 15 0 7 5 0 0
  122. $target arm mcr 15 0 7 7 0 0
  123. # Invalidate all TLBs
  124. $target arm mcr 15 0 8 5 0 0
  125. $target arm mcr 15 0 8 6 0 0
  126. $target arm mcr 15 0 8 7 0 0
  127. $target arm mcr 15 4 8 3 0 0
  128. $target arm mcr 15 4 8 7 0 0
  129. set cp [$target arm mrc 15 0 1 0 0]
  130. echo "SCTRL => [format 0x%x $cp]"
  131. set mask [expr 1 << 29 | 1 << 12 | 1 << 11 | 1 << 2 | 1 << 1 | 1 << 0]
  132. set cp [expr ($cp & ~$mask)]
  133. $target arm mcr 15 0 1 0 0 $cp
  134. echo "SCTRL <= [format 0x%x $cp]"
  135. }
  136. }
  137. proc zynq_boot_ocm_setup { } {
  138. #
  139. # Enable the OCM
  140. #
  141. echo "Zynq Boot OCM setup"
  142. catch {
  143. mww phys 0xF8000008 0xDF0D
  144. mww phys 0xF8000238 0
  145. mww phys 0xF8000910 0xC
  146. }
  147. }
  148. proc zynq_rtems_setup { } {
  149. cache_config l2x 0xF8F02000 8
  150. cortex_a maskisr on
  151. }
  152. proc zynq_restart { wait } {
  153. global _SMP
  154. global _TARGETNAME_0
  155. global _TARGETNAME_1
  156. set target0 $_TARGETNAME_0
  157. set target1 $_TARGETNAME_1
  158. echo "Zynq reset, resetting the board ... "
  159. poll off
  160. #
  161. # Issue the reset via the SLCR
  162. #
  163. catch {
  164. mww phys 0xF8000008 0xDF0D
  165. mww phys 0xF8000200 1
  166. }
  167. echo "Zynq reset waiting for $wait msecs ... "
  168. sleep $wait
  169. #
  170. # Reconnect the DAP etc due to the reset.
  171. #
  172. $target0 cortex_a dbginit
  173. $target0 arm core_state arm
  174. if { $_SMP } {
  175. $target1 arm core_state arm
  176. $target1 cortex_a dbginit
  177. cortex_a smp_off
  178. }
  179. poll on
  180. #
  181. # We can now halt the core.
  182. #
  183. if { $_SMP } {
  184. targets $target1
  185. halt
  186. }
  187. targets $target0
  188. halt
  189. zynq_rtems_setup
  190. }
  191. proc zynq_gdb_attach { target } {
  192. catch {
  193. halt
  194. }
  195. }