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zedboard.py 6.0KB

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  1. #!/usr/bin/env python
  2. from migen_axi.integration.soc_core import SoCCore
  3. from migen_axi.platforms import zedboard
  4. from migen import *
  5. from misoc.interconnect.csr import *
  6. from migen.genlib.resetsync import AsyncResetSynchronizer
  7. from migen.genlib.cdc import MultiReg
  8. from misoc.integration.builder import *
  9. from artiq.gateware import rtio
  10. from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2
  11. from artiq.gateware.rtio.phy import ttl_serdes_7series, ttl_simple
  12. from maxi_dma import MAXI_DMA, DMA_KernelInitiator, DMA_Test
  13. from hp_dma import HP_DMA_READ
  14. from operator import attrgetter
  15. import argparse
  16. import os
  17. class _RTIOCRG(Module, AutoCSR):
  18. def __init__(self):
  19. self._pll_reset = CSRStorage(reset=1)
  20. self._pll_locked = CSRStatus()
  21. self.clock_domains.cd_sys = ClockDomain()
  22. self.clock_domains.cd_rtio = ClockDomain()
  23. # self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
  24. pll_locked = Signal()
  25. rtio_clk = Signal()
  26. rtiox4_clk = Signal()
  27. self.specials += [
  28. Instance("PLLE2_ADV",
  29. p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
  30. p_REF_JITTER1=0.24,
  31. p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
  32. i_CLKIN2=self.cd_sys.clk,
  33. # Warning: CLKINSEL=0 means CLKIN2 is selected
  34. i_CLKINSEL=0,
  35. # VCO @ 1GHz when using 125MHz input
  36. p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
  37. i_CLKFBIN=self.cd_rtio.clk,
  38. i_RST=self._pll_reset.storage,
  39. o_CLKFBOUT=rtio_clk,
  40. # p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
  41. # o_CLKOUT0=rtiox4_clk
  42. ),
  43. Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
  44. # Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
  45. AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
  46. MultiReg(pll_locked, self._pll_locked.status)
  47. ]
  48. def fix_serdes_timing_path(platform):
  49. # ignore timing of path from OSERDESE2 through the pad to ISERDESE2
  50. platform.add_platform_command(
  51. "set_false_path -quiet "
  52. "-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
  53. "-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
  54. "-to [get_pins -filter {{REF_PIN_NAME == D}} "
  55. "-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
  56. )
  57. class Zedboard(SoCCore):
  58. def __init__(self):
  59. plat = zedboard.Platform()
  60. super().__init__(platform=plat)
  61. fclk0 = self.ps7.fclk.clk[0]
  62. self.clock_domains.cd_sys = ClockDomain()
  63. self.specials += Instance("BUFG", i_I=fclk0, o_O=self.cd_sys.clk),
  64. plat.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
  65. plat.add_platform_command("set_input_jitter clk_fpga_0 0.24")
  66. self.evento_stb = Signal()
  67. evento_latched = Signal()
  68. evento_latched_d = Signal()
  69. self.sync += evento_latched.eq(self.ps7.event.o)
  70. self.sync += evento_latched_d.eq(evento_latched)
  71. self.comb += self.evento_stb.eq(evento_latched != evento_latched_d)
  72. self.submodules.hp_dma = HP_DMA_READ(bus=self.ps7.s_axi_hp0)
  73. self.csr_devices.append("hp_dma")
  74. # Debug ports
  75. # pads_b = plat.request("pmod",1)
  76. # ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(self.dma.bus)
  77. # self.comb += pads_b[0].eq(self.dma.trigger_stb)
  78. self.rtio_channels = []
  79. for i in range(4):
  80. pad = plat.request("user_led", i)
  81. phy = ttl_simple.InOut(pad)
  82. self.submodules += phy
  83. self.rtio_channels.append(rtio.Channel.from_phy(phy))
  84. for i in range(4):
  85. led = plat.request("user_led", i+4)
  86. s = Signal()
  87. btn = plat.request("user_btn", i)
  88. self.comb += led.eq(s | btn)
  89. self.comb += s.eq(self.ps7.gpio.o[i])
  90. pads = plat.request("pmod",0)
  91. for i in range(8):
  92. phy = ttl_simple.InOut(pads[i])
  93. self.submodules += phy
  94. self.rtio_channels.append(rtio.Channel.from_phy(phy))
  95. self.add_rtio(self.rtio_channels)
  96. def add_rtio(self, rtio_channels):
  97. self.submodules.rtio_crg = _RTIOCRG()
  98. self.csr_devices.append("rtio_crg")
  99. self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
  100. self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
  101. self.csr_devices.append("rtio_core")
  102. self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
  103. self.csr_devices.append("rtio")
  104. self.submodules.dma = MAXI_DMA(bus=self.ps7.s_axi_acp,
  105. user=self.ps7.s_axi_acp_user,
  106. trigger_stb=self.evento_stb)
  107. self.csr_devices.append("dma")
  108. self.submodules.rtio_dma = DMA_KernelInitiator(engine=self.dma)
  109. self.submodules.cri_con = rtio.CRIInterconnectShared(
  110. [self.rtio.cri, self.rtio_dma.cri],
  111. [self.rtio_core.cri])
  112. self.csr_devices.append("cri_con")
  113. self.platform.add_false_path_constraints(
  114. self.rtio_crg.cd_rtio.clk)
  115. self.comb += self.rtio_crg.cd_sys.clk.eq(self.cd_sys.clk)
  116. def main():
  117. parser = argparse.ArgumentParser()
  118. builder_args(parser)
  119. args = parser.parse_args()
  120. soc = Zedboard()
  121. # TODO:
  122. # builder = Builder(soc, **builder_argdict(args))
  123. # builder.software_packages = []
  124. # root_path = os.path.dirname(os.path.abspath(__file__))
  125. # builder.add_software_package("libm")
  126. # builder.add_software_package("libprintf")
  127. # builder.add_software_package("libunwind")
  128. # builder.add_software_package("libbase")
  129. # builder.add_software_package("runtime", os.path.join(root_path, "firmware/runtime"))
  130. # builder.build()
  131. soc.build()
  132. if __name__ == "__main__":
  133. main()