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test_rtio_dma.py 1.7KB

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  1. #!/usr/bin/env python
  2. from migen import *
  3. from maxi_dma import *
  4. def test(dut):
  5. def delay_cycles(N):
  6. for _ in range(N):
  7. yield
  8. yield from delay_cycles(4)
  9. yield dut.trigger_stb.eq(1)
  10. yield
  11. yield dut.trigger_stb.eq(0)
  12. yield from delay_cycles(2)
  13. assert (yield dut.din_ready)==0
  14. douts = [
  15. (0x2<<32) | (1<< 24) | 1, # address, cmd, channel
  16. 0x55, # timestamp
  17. 0x111111, # Data
  18. 0x0
  19. ]
  20. yield dut.dout_stb.eq(1)
  21. for i in range( (yield dut.out_burst_len) ):
  22. yield dut.dout_index.eq(i)
  23. yield dut.dout.eq(douts[i])
  24. yield
  25. yield dut.dout_stb.eq(0)
  26. # yield dut.h.cri.o_status.eq(0x3)
  27. yield from delay_cycles(10)
  28. yield dut.h.cri.i_data.eq(1)
  29. yield dut.h.cri.i_timestamp.eq(2)
  30. yield dut.h.cri.i_status.eq(4)
  31. while True:
  32. if (yield dut.din_ready):
  33. break
  34. yield
  35. yield dut.din_stb.eq(1)
  36. print("Got: ")
  37. dins = []
  38. for i in range( (yield dut.in_burst_len) ):
  39. yield dut.din_index.eq(i)
  40. yield
  41. dins.append( (yield dut.din) )
  42. yield dut.din_stb.eq(0)
  43. print(dins)
  44. class Wrapper(Module):
  45. def __init__(self):
  46. self.dout_stb = Signal()
  47. self.din_stb = Signal()
  48. self.dout_index = Signal(max=16)
  49. self.din_index = Signal(max=16)
  50. self.din_ready = Signal()
  51. self.dout = Signal(64)
  52. self.din = Signal(64)
  53. self.out_burst_len = Signal(max=16)
  54. self.in_burst_len = Signal(max=16)
  55. self.trigger_stb = Signal()
  56. self.submodules.h = DMA_KernelInitiator(self)
  57. if __name__ == "__main__":
  58. dut = Wrapper()
  59. run_simulation(dut, test(dut), vcd_name="test_rtio_dma.vcd", clocks={"sys": 8})