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test_maxi_dma.py 1.5KB

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  1. #!/usr/bin/env python
  2. from migen import *
  3. from maxi_dma import *
  4. def test_basic(dut):
  5. yield from dut.engine.addr_base.write(0x12340)
  6. for _ in range(5):
  7. yield
  8. yield dut.engine.bus.ar.ready.eq(1)
  9. yield
  10. yield dut.trigger.eq(1)
  11. while True:
  12. if (yield dut.engine.bus.ar.valid):
  13. break
  14. yield
  15. yield dut.engine.bus.ar.ready.eq(0)
  16. yield dut.trigger.eq(0)
  17. def deliver_read_word(w, last=False):
  18. yield dut.engine.bus.r.data.eq(w)
  19. yield dut.engine.bus.r.valid.eq(1)
  20. if last:
  21. yield dut.engine.bus.r.last.eq(1)
  22. for _ in range(100):
  23. yield
  24. if (yield dut.engine.bus.r.ready):
  25. yield dut.engine.bus.r.valid.eq(0)
  26. yield dut.engine.bus.r.last.eq(0)
  27. break
  28. yield
  29. for i in range(4):
  30. yield from deliver_read_word(2*i | (2*i+1)<<32, last=i==3)
  31. for _ in range(5):
  32. yield
  33. while True:
  34. if (yield dut.engine.bus.aw.valid):
  35. break
  36. yield
  37. yield dut.engine.bus.aw.ready.eq(1)
  38. yield
  39. yield dut.engine.bus.aw.ready.eq(0)
  40. yield dut.engine.bus.w.ready.eq(1)
  41. for _ in range(10):
  42. yield
  43. class Wrapper(Module):
  44. def __init__(self):
  45. self.trigger = Signal()
  46. self.submodules.engine = MAXI_DMA(trigger_stb=self.trigger)
  47. self.submodules.dma_test = DMA_Test(self.engine)
  48. if __name__ == "__main__":
  49. dut = Wrapper()
  50. run_simulation(dut, test_basic(dut), vcd_name="test.vcd", clocks={"sys": 8})