use log::{info, warn};
use libboard_zynq::{timer::GlobalTimer};
use embedded_hal::blocking::delay::DelayMs;
use libconfig::Config;
use libboard_artiq::pl;
use crate::i2c;

#[cfg(has_si5324)]
use libboard_artiq::si5324;


#[derive(Debug, PartialEq, Copy, Clone)]
#[allow(non_camel_case_types)]
pub enum RtioClock {
    Int_125,
    Int_100,
    Int_150,
    Ext0_Bypass,
    Ext0_Synth0_10to125,
    Ext0_Synth0_100to125,
    Ext0_Synth0_125to125,
}

fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
    if let Ok(clk) = cfg.read_str("rtio_clock") {
        match clk.as_ref() {
            "int_125" => RtioClock::Int_125,
            "int_100" => RtioClock::Int_100,
            "int_150" => RtioClock::Int_150,
            "ext0_bypass" => RtioClock::Ext0_Bypass,
            "ext0_synth0_10to125" => RtioClock::Ext0_Synth0_10to125,
            "ext0_synth0_100to125" => RtioClock::Ext0_Synth0_100to125,
            "ext0_synth0_125to125" => RtioClock::Ext0_Synth0_125to125,
            _ => RtioClock::Int_125
        }
    }
    else {
        RtioClock::Int_125
    }
}


fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
    #[cfg(has_rtio_crg_clock_sel)]
    let clock_sel = match _clk {
        RtioClock::Ext0_Bypass => { 
            info!("using bypassed external clock");
            1
        },
        x => {
            info!("using clock: {:?}", x);
            0
        }
    };

    loop {
        unsafe {
            pl::csr::rtio_crg::pll_reset_write(1);
            #[cfg(has_rtio_crg_clock_sel)]
            pl::csr::rtio_crg::clock_sel_write(clock_sel);
            pl::csr::rtio_crg::pll_reset_write(0);
        }
        timer.delay_ms(1);
        let locked = unsafe { pl::csr::rtio_crg::pll_locked_read() != 0 };
        if locked {
            info!("RTIO PLL locked");
            break;
        } else {
            warn!("RTIO PLL failed to lock, retrying...");
            timer.delay_ms(500);
        }
    }

    unsafe {
        pl::csr::rtio_core::reset_phy_write(1);
    }
}

#[cfg(has_drtio)]
fn init_drtio(timer: &mut GlobalTimer)
{
    unsafe {
        pl::csr::drtio_transceiver::stable_clkin_write(1);
    }
    timer.delay_ms(2); // wait for CPLL/QPLL lock
    unsafe {
        pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
    }
}

#[cfg(has_si5324)]
fn setup_si5324(timer: &mut GlobalTimer, clk: RtioClock) {
    let mut si5324_settings: Option<si5324::FrequencySettings> = None;
    // 125MHz output, from crystal, 7 Hz
    if si5324_settings.is_none() || clk == RtioClock::Int_125 {
        info!("using internal 125MHz RTIO clock");
        si5324_settings = Some(si5324::FrequencySettings {
            n1_hs  : 10,
            nc1_ls : 4,
            n2_hs  : 10,
            n2_ls  : 19972,
            n31    : 4565,
            n32    : 4565,
            bwsel  : 4,
            crystal_ref: true
        });
    }
    si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() },
        &si5324_settings.unwrap(), si5324::Input::Ckin2, timer).expect("cannot initialize Si5324");
}

pub fn init(timer: &mut GlobalTimer, cfg: &Config) {

    let clk = get_rtio_clock_cfg(cfg);
    #[cfg(has_si5324)]
    setup_si5324(timer, clk);

    #[cfg(has_drtio)]
    init_drtio(timer);

    init_rtio(timer, clk);

}