M-Labs/artiq-zynq
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Extend gateware ident for zynq #346

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sb10q merged 2 commits from mwojcik/artiq-zynq:gateware_ident into master 2024-12-11 11:43:52 +08:00
Conversation 1 Commits 2 Files Changed 5 +37 -23
5 changed files with 37 additions and 23 deletions
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4
flake.nix
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@ -11,6 +11,7 @@
zynqpkgs = zynq-rs.packages.x86_64-linux; zynqpkgs = zynq-rs.packages.x86_64-linux;
artiqpkgs = artiq.packages.x86_64-linux; artiqpkgs = artiq.packages.x86_64-linux;
llvmPackages_11 = zynq-rs.llvmPackages_11; llvmPackages_11 = zynq-rs.llvmPackages_11;
zynqRev = self.sourceInfo.rev or "unknown";
rust = zynq-rs.rust; rust = zynq-rs.rust;
rustPlatform = zynq-rs.rustPlatform; rustPlatform = zynq-rs.rustPlatform;
@ -137,6 +138,7 @@
llvmPackages_11.clang-unwrapped llvmPackages_11.clang-unwrapped
]; ];
buildPhase = '' buildPhase = ''
export ZYNQ_REV=${zynqRev}
export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library" export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include" export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"
export CARGO_HOME=$(mktemp -d cargo-home.XXX) export CARGO_HOME=$(mktemp -d cargo-home.XXX)
@ -164,6 +166,7 @@
]; ];
} }
'' ''
export ZYNQ_REV=${zynqRev}
python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json} python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
mkdir -p $out $out/nix-support mkdir -p $out $out/nix-support
cp build/top.bit $out cp build/top.bit $out
@ -386,6 +389,7 @@
binutils-arm binutils-arm
pre-commit pre-commit
]; ];
ZYNQ_REV="${zynqRev}";
sb10q commented 2024-12-05 17:07:59 +08:00
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VERSIONEER_ is historical. Just call it ZYNQ_REV.

``VERSIONEER_`` is historical. Just call it ``ZYNQ_REV``.
XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library"; XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"; CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include";
ZYNQ_RS = "${zynq-rs}"; ZYNQ_RS = "${zynq-rs}";

10
src/gateware/config.py
View File

@ -1,5 +1,15 @@
import os
from artiq._version import get_version
from misoc.integration import cpu_interface from misoc.integration import cpu_interface
def generate_ident(variant):
return "{}+{};{}".format(
get_version().split(".")[0],
os.getenv("ZYNQ_REV", default="unknown")[:8],
variant,
)
def write_csr_file(soc, filename): def write_csr_file(soc, filename):
with open(filename, "w") as f: with open(filename, "w") as f:
f.write(cpu_interface.get_csr_rust( f.write(cpu_interface.get_csr_rust(

4
src/gateware/ebaz4205.py
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@ -7,7 +7,7 @@ import dma
from artiq.gateware import rtio from artiq.gateware import rtio
from artiq.gateware.rtio.phy import spi2, ttl_simple from artiq.gateware.rtio.phy import spi2, ttl_simple
from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
from config import write_csr_file, write_mem_file, write_rustc_cfg_file from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
from migen import * from migen import *
from migen.build.generic_platform import IOStandard, Misc, Pins, Subsignal from migen.build.generic_platform import IOStandard, Misc, Pins, Subsignal
from migen.build.platforms import ebaz4205 from migen.build.platforms import ebaz4205
@ -125,7 +125,7 @@ class EBAZ4205(SoCCore):
"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]" "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
) )
ident = self.__class__.__name__ ident = generate_ident(self.__class__.__name__)
if self.acpki: if self.acpki:
sb10q commented 2024-12-05 17:08:40 +08:00
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I don't think we need the ARTIQ version? It is defined by the flake.lock of the Zynq revision.

I don't think we need the ARTIQ version? It is defined by the flake.lock of the Zynq revision.
mwojcik commented 2024-12-05 17:44:29 +08:00
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Exact revision maybe not, but I think it would be valuable to at least have the major number to check at a glance.

Exact revision maybe not, but I think it would be valuable to at least have the major number to check at a glance.
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)

16
src/gateware/kasli_soc.py
View File

@ -24,10 +24,10 @@ from artiq.gateware.wrpll import wrpll
import dma import dma
import analyzer import analyzer
import acpki import acpki as acpki_lib
import drtio_aux_controller import drtio_aux_controller
import zynq_clocking import zynq_clocking
from config import write_csr_file, write_mem_file, write_rustc_cfg_file from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
eem_iostandard_dict = { eem_iostandard_dict = {
0: "LVDS_25", 0: "LVDS_25",
@ -115,7 +115,7 @@ class GenericStandalone(SoCCore):
platform.toolchain.bitstream_commands.extend([ platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
]) ])
ident = description["variant"] ident = generate_ident(description["variant"])
if self.acpki: if self.acpki:
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -184,7 +184,7 @@ class GenericStandalone(SoCCore):
if self.acpki: if self.acpki:
self.config["KI_IMPL"] = "acp" self.config["KI_IMPL"] = "acp"
self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
bus=self.ps7.s_axi_acp, bus=self.ps7.s_axi_acp,
user=self.ps7.s_axi_acp_user, user=self.ps7.s_axi_acp_user,
evento=self.ps7.event.o) evento=self.ps7.event.o)
@ -229,7 +229,7 @@ class GenericMaster(SoCCore):
platform.toolchain.bitstream_commands.extend([ platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
]) ])
ident = description["variant"] ident = generate_ident(description["variant"])
if self.acpki: if self.acpki:
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -349,7 +349,7 @@ class GenericMaster(SoCCore):
if self.acpki: if self.acpki:
self.config["KI_IMPL"] = "acp" self.config["KI_IMPL"] = "acp"
self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
bus=self.ps7.s_axi_acp, bus=self.ps7.s_axi_acp,
user=self.ps7.s_axi_acp_user, user=self.ps7.s_axi_acp_user,
evento=self.ps7.event.o) evento=self.ps7.event.o)
@ -438,7 +438,7 @@ class GenericSatellite(SoCCore):
platform.toolchain.bitstream_commands.extend([ platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
]) ])
ident = description["variant"] ident = generate_ident(description["variant"])
if self.acpki: if self.acpki:
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -544,7 +544,7 @@ class GenericSatellite(SoCCore):
if self.acpki: if self.acpki:
self.config["KI_IMPL"] = "acp" self.config["KI_IMPL"] = "acp"
self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
bus=self.ps7.s_axi_acp, bus=self.ps7.s_axi_acp,
user=self.ps7.s_axi_acp_user, user=self.ps7.s_axi_acp_user,
evento=self.ps7.event.o) evento=self.ps7.event.o)

8
src/gateware/zc706.py
View File

@ -25,7 +25,7 @@ import analyzer
import acpki import acpki
import drtio_aux_controller import drtio_aux_controller
import zynq_clocking import zynq_clocking
from config import write_csr_file, write_mem_file, write_rustc_cfg_file from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
class SMAClkinForward(Module): class SMAClkinForward(Module):
def __init__(self, platform): def __init__(self, platform):
@ -130,7 +130,7 @@ class ZC706(SoCCore):
platform = zc706.Platform() platform = zc706.Platform()
prepare_zc706_platform(platform) prepare_zc706_platform(platform)
ident = self.__class__.__name__ ident = generate_ident(self.__class__.__name__)
if self.acpki: if self.acpki:
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -203,7 +203,7 @@ class _MasterBase(SoCCore):
platform = zc706.Platform() platform = zc706.Platform()
prepare_zc706_platform(platform) prepare_zc706_platform(platform)
ident = self.__class__.__name__ ident = generate_ident(self.__class__.__name__)
if self.acpki: if self.acpki:
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@ -344,7 +344,7 @@ class _SatelliteBase(SoCCore):
platform = zc706.Platform() platform = zc706.Platform()
prepare_zc706_platform(platform) prepare_zc706_platform(platform)
ident = self.__class__.__name__ ident = generate_ident(self.__class__.__name__)
if self.acpki: if self.acpki:
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)