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Set FCLK0 for EBAZ4205 #337

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sb10q merged 2 commits from newell/artiq-zynq:set-fclk0 into master 2024-11-17 10:08:44 +08:00
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1 changed files with 1 additions and 9 deletions
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src/runtime/src/rtio_clocking.rs
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@ -425,14 +425,6 @@ fn set_fclk0_freq(clk: RtioClock, cfg: &Config) {
target_freq = 125_000_000;
divisor0 = 8;
}
RtioClock::Int_150 => {
target_freq = 150_000_000;
divisor0 = 7; // Closest approximation to 150 MHz
warn!(
"Closest achievable FCLK0 frequency for RTIO Clock 150 MHz is {:.2} MHz (divider 7).",
io_pll_freq as f64 / divisor0 as f64
);
}
_ => {
warn!("Unsupported RTIO Clock: '{:?}'", clk);
return;
@ -479,7 +471,7 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
#[cfg(feature = "target_ebaz4205")]
{
match clk {
RtioClock::Int_100 | RtioClock::Int_125 | RtioClock::Int_150 => {
RtioClock::Int_100 | RtioClock::Int_125 => {
set_fclk0_freq(clk, cfg);
}
_ => {} // Not set for external clocks