Set FCLK0 for EBAZ4205 #337
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Reference: M-Labs/artiq-zynq#337
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EBAZ4205 uses FCLK0 as the RTIO clock.
This branch makes sure to set FCLK0 to the correct frequency.
Note:
If the user has the RTIO clock set to 150 MHz the closest we can get to this is approximately 142 MHz, of which the user is warned, using a divider of 7 on the hardcoded
IoPll
frequency which is set inzynq-rs
(seeszl/src/main.rs
) to1_000_000_000
.If the user modifies the gateware to use an external clock, FCLK0 is not used.
Is the divider setting glitch-free? Otherwise this needs to happen while the RTIO core is under reset.
I'm not sure if the 142MHz setting is any useful, I would just make "150MHz" unsupported. The FPGA timing constraints otherwise also need to be adjusted to meet timing at 142MHz.
According to Figure 25-10, page 737, of the Zynq 7000 SoC Technical Reference Manual UG585 (v1.14), these dividers are glitch-free.
It may be best to add documentation to the manual stating that
int_150
is not supported for EBAZ4205.