Set FCLK0 for EBAZ4205 #337

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sb10q merged 2 commits from newell/artiq-zynq:set-fclk0 into master 2024-11-17 10:08:44 +08:00
Contributor

EBAZ4205 uses FCLK0 as the RTIO clock.

This branch makes sure to set FCLK0 to the correct frequency.

Note:

  • If the user has the RTIO clock set to 150 MHz the closest we can get to this is approximately 142 MHz, of which the user is warned, using a divider of 7 on the hardcoded IoPll frequency which is set in zynq-rs (see szl/src/main.rs) to 1_000_000_000.

  • If the user modifies the gateware to use an external clock, FCLK0 is not used.

EBAZ4205 uses FCLK0 as the RTIO clock. This branch makes sure to set FCLK0 to the correct frequency. Note: * If the user has the RTIO clock set to 150 MHz the closest we can get to this is approximately 142 MHz, of which the user is warned, using a divider of 7 on the hardcoded `IoPll` frequency which is set in `zynq-rs` (see `szl/src/main.rs`) to `1_000_000_000`. * If the user modifies the gateware to use an external clock, FCLK0 is not used.
newell added 1 commit 2024-11-17 06:52:48 +08:00
Owner

Is the divider setting glitch-free? Otherwise this needs to happen while the RTIO core is under reset.
I'm not sure if the 142MHz setting is any useful, I would just make "150MHz" unsupported. The FPGA timing constraints otherwise also need to be adjusted to meet timing at 142MHz.

Is the divider setting glitch-free? Otherwise this needs to happen while the RTIO core is under reset. I'm not sure if the 142MHz setting is any useful, I would just make "150MHz" unsupported. The FPGA timing constraints otherwise also need to be adjusted to meet timing at 142MHz.
newell added 1 commit 2024-11-17 10:04:52 +08:00
Author
Contributor

Is the divider setting glitch-free? Otherwise this needs to happen while the RTIO core is under reset.
I'm not sure if the 142MHz setting is any useful, I would just make "150MHz" unsupported. The FPGA timing constraints otherwise also need to be adjusted to meet timing at 142MHz.

According to Figure 25-10, page 737, of the Zynq 7000 SoC Technical Reference Manual UG585 (v1.14), these dividers are glitch-free.

> Is the divider setting glitch-free? Otherwise this needs to happen while the RTIO core is under reset. > I'm not sure if the 142MHz setting is any useful, I would just make "150MHz" unsupported. The FPGA timing constraints otherwise also need to be adjusted to meet timing at 142MHz. According to Figure 25-10, page 737, of the Zynq 7000 SoC Technical Reference Manual UG585 (v1.14), these dividers are glitch-free.
Author
Contributor

It may be best to add documentation to the manual stating that int_150 is not supported for EBAZ4205.

It may be best to add documentation to the manual stating that `int_150` is not supported for EBAZ4205.
sb10q merged commit 2c633409b8 into master 2024-11-17 10:08:44 +08:00
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Reference: M-Labs/artiq-zynq#337
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