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gateware: Add default TTLs to EBAZ4205 #335

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sb10q merged 2 commits from newell/artiq-zynq:ebaz4205-ttl into master 2024-11-16 10:40:49 +08:00
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1 changed files with 2 additions and 2 deletions
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src/gateware/ebaz4205.py
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@ -5,7 +5,7 @@ import argparse
import analyzer import analyzer
import dma import dma
from artiq.gateware import rtio from artiq.gateware import rtio
from artiq.gateware.rtio.phy import dds, spi2, ttl_simple from artiq.gateware.rtio.phy import spi2, ttl_simple
from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
from config import write_csr_file, write_mem_file, write_rustc_cfg_file from config import write_csr_file, write_mem_file, write_rustc_cfg_file
from migen import * from migen import *
@ -195,7 +195,7 @@ class EBAZ4205(SoCCore):
for i in range(14): for i in range(14):
print("TTL at RTIO channel 0x{:06x}".format(len(self.rtio_channels))) print("TTL at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
ttl = self.platform.request("ttl", i) ttl = self.platform.request("ttl", i)
phy = ttl_simple.Output(ttl) phy = ttl_simple.InOut(ttl)
self.submodules += phy self.submodules += phy
self.rtio_channels.append(rtio.Channel.from_phy(phy)) self.rtio_channels.append(rtio.Channel.from_phy(phy))