Support CoreMgmt over DRTIO on Zynq Devices #323
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@ -559,7 +559,9 @@ name = "satman"
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version = "0.0.0"
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version = "0.0.0"
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dependencies = [
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dependencies = [
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"build_zynq",
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"build_zynq",
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"byteorder",
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"core_io",
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"core_io",
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"crc",
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"cslice",
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"cslice",
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"embedded-hal",
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"embedded-hal",
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"io",
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"io",
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@ -288,6 +288,77 @@ pub enum Packet {
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SubkernelMessageAck {
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SubkernelMessageAck {
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destination: u8,
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destination: u8,
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},
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},
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CoreMgmtGetLogRequest {
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destination: u8,
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clear: bool,
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},
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CoreMgmtClearLogRequest {
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destination: u8,
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},
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CoreMgmtSetLogLevelRequest {
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destination: u8,
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log_level: u8,
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},
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CoreMgmtSetUartLogLevelRequest {
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destination: u8,
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log_level: u8,
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},
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CoreMgmtConfigReadRequest {
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destination: u8,
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length: u16,
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key: [u8; MASTER_PAYLOAD_MAX_SIZE],
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},
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CoreMgmtConfigReadContinue {
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destination: u8,
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},
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CoreMgmtConfigWriteRequest {
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destination: u8,
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last: bool,
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length: u16,
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data: [u8; MASTER_PAYLOAD_MAX_SIZE],
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},
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CoreMgmtConfigRemoveRequest {
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destination: u8,
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length: u16,
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key: [u8; MASTER_PAYLOAD_MAX_SIZE],
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},
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CoreMgmtConfigEraseRequest {
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destination: u8,
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},
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CoreMgmtRebootRequest {
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destination: u8,
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},
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CoreMgmtAllocatorDebugRequest {
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destination: u8,
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},
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CoreMgmtFlashRequest {
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destination: u8,
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payload_length: u32,
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},
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CoreMgmtFlashAddDataRequest {
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destination: u8,
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last: bool,
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length: u16,
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data: [u8; MASTER_PAYLOAD_MAX_SIZE],
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},
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CoreMgmtDropLinkAck {
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destination: u8,
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},
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CoreMgmtDropLink,
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CoreMgmtGetLogReply {
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last: bool,
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length: u16,
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data: [u8; SAT_PAYLOAD_MAX_SIZE],
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},
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CoreMgmtConfigReadReply {
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last: bool,
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length: u16,
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value: [u8; SAT_PAYLOAD_MAX_SIZE],
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},
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CoreMgmtReply {
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succeeded: bool,
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},
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}
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}
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impl Packet {
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impl Packet {
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@ -565,6 +636,115 @@ impl Packet {
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destination: reader.read_u8()?,
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destination: reader.read_u8()?,
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},
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},
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0xd0 => Packet::CoreMgmtGetLogRequest {
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destination: reader.read_u8()?,
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clear: reader.read_bool()?,
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},
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0xd1 => Packet::CoreMgmtClearLogRequest {
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destination: reader.read_u8()?,
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},
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0xd2 => Packet::CoreMgmtSetLogLevelRequest {
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destination: reader.read_u8()?,
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log_level: reader.read_u8()?,
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},
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0xd3 => Packet::CoreMgmtSetUartLogLevelRequest {
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destination: reader.read_u8()?,
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log_level: reader.read_u8()?,
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},
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0xd4 => {
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let destination = reader.read_u8()?;
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let length = reader.read_u16()?;
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let mut key: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
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reader.read_exact(&mut key[0..length as usize])?;
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Packet::CoreMgmtConfigReadRequest {
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destination: destination,
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length: length,
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key: key,
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}
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}
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0xd5 => Packet::CoreMgmtConfigReadContinue {
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destination: reader.read_u8()?,
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},
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0xd6 => {
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let destination = reader.read_u8()?;
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let last = reader.read_bool()?;
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let length = reader.read_u16()?;
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let mut data: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
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reader.read_exact(&mut data[0..length as usize])?;
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Packet::CoreMgmtConfigWriteRequest {
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destination: destination,
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last: last,
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length: length,
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data: data,
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}
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}
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0xd7 => {
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let destination = reader.read_u8()?;
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let length = reader.read_u16()?;
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let mut key: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
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reader.read_exact(&mut key[0..length as usize])?;
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Packet::CoreMgmtConfigRemoveRequest {
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destination: destination,
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length: length,
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key: key,
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}
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}
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0xd8 => Packet::CoreMgmtConfigEraseRequest {
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destination: reader.read_u8()?,
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},
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0xd9 => Packet::CoreMgmtRebootRequest {
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destination: reader.read_u8()?,
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},
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0xda => Packet::CoreMgmtAllocatorDebugRequest {
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destination: reader.read_u8()?,
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},
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0xdb => Packet::CoreMgmtFlashRequest {
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destination: reader.read_u8()?,
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payload_length: reader.read_u32()?,
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},
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0xdc => {
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let destination = reader.read_u8()?;
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let last = reader.read_bool()?;
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let length = reader.read_u16()?;
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let mut data: [u8; MASTER_PAYLOAD_MAX_SIZE] = [0; MASTER_PAYLOAD_MAX_SIZE];
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reader.read_exact(&mut data[0..length as usize])?;
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Packet::CoreMgmtFlashAddDataRequest {
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destination: destination,
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last: last,
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length: length,
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data: data,
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}
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}
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0xdd => Packet::CoreMgmtDropLinkAck {
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destination: reader.read_u8()?,
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},
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0xde => Packet::CoreMgmtDropLink,
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0xdf => {
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let last = reader.read_bool()?;
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let length = reader.read_u16()?;
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let mut data: [u8; SAT_PAYLOAD_MAX_SIZE] = [0; SAT_PAYLOAD_MAX_SIZE];
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reader.read_exact(&mut data[0..length as usize])?;
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Packet::CoreMgmtGetLogReply {
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last: last,
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length: length,
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data: data,
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}
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}
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0xe0 => {
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let last = reader.read_bool()?;
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let length = reader.read_u16()?;
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let mut value: [u8; SAT_PAYLOAD_MAX_SIZE] = [0; SAT_PAYLOAD_MAX_SIZE];
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reader.read_exact(&mut value[0..length as usize])?;
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Packet::CoreMgmtConfigReadReply {
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last: last,
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length: length,
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value: value,
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}
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}
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0xe1 => Packet::CoreMgmtReply {
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succeeded: reader.read_bool()?,
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},
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ty => return Err(Error::UnknownPacket(ty)),
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ty => return Err(Error::UnknownPacket(ty)),
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})
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})
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}
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}
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@ -942,6 +1122,115 @@ impl Packet {
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writer.write_u8(0xcc)?;
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writer.write_u8(0xcc)?;
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writer.write_u8(destination)?;
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writer.write_u8(destination)?;
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}
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}
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Packet::CoreMgmtGetLogRequest { destination, clear } => {
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writer.write_u8(0xd0)?;
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writer.write_u8(destination)?;
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writer.write_bool(clear)?;
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}
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Packet::CoreMgmtClearLogRequest { destination } => {
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writer.write_u8(0xd1)?;
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writer.write_u8(destination)?;
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}
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Packet::CoreMgmtSetLogLevelRequest { destination, log_level } => {
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writer.write_u8(0xd2)?;
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writer.write_u8(destination)?;
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writer.write_u8(log_level)?;
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}
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Packet::CoreMgmtSetUartLogLevelRequest { destination, log_level } => {
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writer.write_u8(0xd3)?;
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writer.write_u8(destination)?;
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writer.write_u8(log_level)?;
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}
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Packet::CoreMgmtConfigReadRequest {
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destination,
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length,
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key,
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} => {
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writer.write_u8(0xd4)?;
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writer.write_u8(destination)?;
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writer.write_u16(length)?;
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writer.write_all(&key[0..length as usize])?;
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}
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Packet::CoreMgmtConfigReadContinue { destination } => {
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writer.write_u8(0xd5)?;
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writer.write_u8(destination)?;
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}
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Packet::CoreMgmtConfigWriteRequest {
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destination,
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last,
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length,
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data,
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} => {
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writer.write_u8(0xd6)?;
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writer.write_u8(destination)?;
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writer.write_bool(last)?;
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writer.write_u16(length)?;
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writer.write_all(&data[0..length as usize])?;
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}
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Packet::CoreMgmtConfigRemoveRequest {
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destination,
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length,
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key,
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} => {
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writer.write_u8(0xd7)?;
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writer.write_u8(destination)?;
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writer.write_u16(length)?;
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writer.write_all(&key[0..length as usize])?;
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}
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Packet::CoreMgmtConfigEraseRequest { destination } => {
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writer.write_u8(0xd8)?;
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writer.write_u8(destination)?;
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}
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Packet::CoreMgmtRebootRequest { destination } => {
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writer.write_u8(0xd9)?;
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writer.write_u8(destination)?;
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}
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Packet::CoreMgmtAllocatorDebugRequest { destination } => {
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writer.write_u8(0xda)?;
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writer.write_u8(destination)?;
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}
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Packet::CoreMgmtFlashRequest {
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destination,
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payload_length,
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} => {
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writer.write_u8(0xdb)?;
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writer.write_u8(destination)?;
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writer.write_u32(payload_length)?;
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}
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Packet::CoreMgmtFlashAddDataRequest {
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destination,
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last,
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length,
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data,
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} => {
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writer.write_u8(0xdc)?;
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writer.write_u8(destination)?;
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writer.write_bool(last)?;
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writer.write_u16(length)?;
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writer.write_all(&data[..length as usize])?;
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}
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Packet::CoreMgmtDropLinkAck { destination } => {
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writer.write_u8(0xdd)?;
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writer.write_u8(destination)?;
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}
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Packet::CoreMgmtDropLink => writer.write_u8(0xde)?,
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Packet::CoreMgmtGetLogReply { last, length, data } => {
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writer.write_u8(0xdf)?;
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writer.write_bool(last)?;
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writer.write_u16(length)?;
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writer.write_all(&data[0..length as usize])?;
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}
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Packet::CoreMgmtConfigReadReply { last, length, value } => {
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writer.write_u8(0xe0)?;
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writer.write_bool(last)?;
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writer.write_u16(length)?;
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writer.write_all(&value[0..length as usize])?;
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}
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Packet::CoreMgmtReply { succeeded } => {
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writer.write_u8(0xe1)?;
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writer.write_bool(succeeded)?;
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}
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}
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}
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Ok(())
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Ok(())
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}
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}
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@ -978,7 +1267,8 @@ impl Packet {
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| Packet::SubkernelLoadRunReply { .. }
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| Packet::SubkernelLoadRunReply { .. }
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| Packet::SubkernelMessageAck { .. }
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| Packet::SubkernelMessageAck { .. }
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| Packet::DmaPlaybackStatus { .. }
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| Packet::DmaPlaybackStatus { .. }
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| Packet::SubkernelFinished { .. } => false,
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| Packet::SubkernelFinished { .. }
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| Packet::CoreMgmtDropLinkAck { .. } => false,
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_ => true,
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_ => true,
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}
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}
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}
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}
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@ -21,6 +21,7 @@ cslice = "0.3"
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log = "0.4"
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log = "0.4"
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embedded-hal = "0.2"
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embedded-hal = "0.2"
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core_io = { version = "0.1", features = ["collections"] }
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core_io = { version = "0.1", features = ["collections"] }
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crc = { version = "1.7", default-features = false }
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byteorder = { version = "1.3", default-features = false }
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byteorder = { version = "1.3", default-features = false }
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void = { version = "1", default-features = false }
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void = { version = "1", default-features = false }
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||||||
futures = { version = "0.3", default-features = false, features = ["async-await"] }
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futures = { version = "0.3", default-features = false, features = ["async-await"] }
|
||||||
|
|
|
@ -785,7 +785,11 @@ pub fn main(timer: GlobalTimer, cfg: Config) {
|
||||||
|
|
||||||
let cfg = Rc::new(cfg);
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let cfg = Rc::new(cfg);
|
||||||
let restart_idle = Rc::new(Semaphore::new(1, 1));
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let restart_idle = Rc::new(Semaphore::new(1, 1));
|
||||||
mgmt::start(cfg.clone(), restart_idle.clone());
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mgmt::start(
|
||||||
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cfg.clone(),
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||||||
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restart_idle.clone(),
|
||||||
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Some(mgmt::DrtioContext(aux_mutex.clone(), drtio_routing_table.clone(), timer)),
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);
|
||||||
|
|
||||||
task::spawn(async move {
|
task::spawn(async move {
|
||||||
let connection = Rc::new(Semaphore::new(1, 1));
|
let connection = Rc::new(Semaphore::new(1, 1));
|
||||||
|
@ -911,7 +915,7 @@ pub fn soft_panic_main(timer: GlobalTimer, cfg: Config) -> ! {
|
||||||
Sockets::init(32);
|
Sockets::init(32);
|
||||||
|
|
||||||
let dummy = Rc::new(Semaphore::new(0, 1));
|
let dummy = Rc::new(Semaphore::new(0, 1));
|
||||||
mgmt::start(Rc::new(cfg), dummy);
|
mgmt::start(Rc::new(cfg), dummy, None);
|
||||||
|
|
||||||
// getting eth settings disables the LED as it resets GPIO
|
// getting eth settings disables the LED as it resets GPIO
|
||||||
// need to re-enable it here
|
// need to re-enable it here
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -577,7 +577,7 @@ pub mod drtio {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
async fn partition_data<PacketF, HandlerF>(
|
pub async fn partition_data<PacketF, HandlerF>(
|
||||||
linkno: u8,
|
linkno: u8,
|
||||||
aux_mutex: &Rc<Mutex<bool>>,
|
aux_mutex: &Rc<Mutex<bool>>,
|
||||||
routing_table: &RoutingTable,
|
routing_table: &RoutingTable,
|
||||||
|
|
|
@ -15,7 +15,9 @@ build_zynq = { path = "../libbuild_zynq" }
|
||||||
|
|
||||||
[dependencies]
|
[dependencies]
|
||||||
log = { version = "0.4", default-features = false }
|
log = { version = "0.4", default-features = false }
|
||||||
|
byteorder = { version = "1.3", default-features = false }
|
||||||
core_io = { version = "0.1", features = ["collections"] }
|
core_io = { version = "0.1", features = ["collections"] }
|
||||||
|
crc = { version = "1.7", default-features = false }
|
||||||
cslice = "0.3"
|
cslice = "0.3"
|
||||||
embedded-hal = "0.2"
|
embedded-hal = "0.2"
|
||||||
|
|
||||||
|
|
|
@ -4,7 +4,9 @@
|
||||||
|
|
||||||
#[macro_use]
|
#[macro_use]
|
||||||
extern crate log;
|
extern crate log;
|
||||||
|
extern crate byteorder;
|
||||||
extern crate core_io;
|
extern crate core_io;
|
||||||
|
extern crate crc;
|
||||||
extern crate cslice;
|
extern crate cslice;
|
||||||
extern crate embedded_hal;
|
extern crate embedded_hal;
|
||||||
|
|
||||||
|
@ -38,16 +40,18 @@ use libboard_artiq::{drtio_routing, drtioaux,
|
||||||
pl::csr};
|
pl::csr};
|
||||||
#[cfg(feature = "target_kasli_soc")]
|
#[cfg(feature = "target_kasli_soc")]
|
||||||
use libboard_zynq::error_led::ErrorLED;
|
use libboard_zynq::error_led::ErrorLED;
|
||||||
use libboard_zynq::{i2c::I2c, print, println, time::Milliseconds, timer::GlobalTimer};
|
use libboard_zynq::{i2c::I2c, print, println, slcr, time::Milliseconds, timer::GlobalTimer};
|
||||||
use libconfig::Config;
|
use libconfig::Config;
|
||||||
use libcortex_a9::{l2c::enable_l2_cache, regs::MPIDR};
|
use libcortex_a9::{l2c::enable_l2_cache, regs::MPIDR};
|
||||||
use libregister::RegisterR;
|
use libregister::RegisterR;
|
||||||
use libsupport_zynq::{exception_vectors, ram};
|
use libsupport_zynq::{exception_vectors, ram};
|
||||||
|
use mgmt::Manager as CoreManager;
|
||||||
use routing::Router;
|
use routing::Router;
|
||||||
use subkernel::Manager as KernelManager;
|
use subkernel::Manager as KernelManager;
|
||||||
|
|
||||||
mod analyzer;
|
mod analyzer;
|
||||||
mod dma;
|
mod dma;
|
||||||
|
mod mgmt;
|
||||||
mod repeater;
|
mod repeater;
|
||||||
mod routing;
|
mod routing;
|
||||||
mod subkernel;
|
mod subkernel;
|
||||||
|
@ -149,6 +153,7 @@ fn process_aux_packet(
|
||||||
dma_manager: &mut DmaManager,
|
dma_manager: &mut DmaManager,
|
||||||
analyzer: &mut Analyzer,
|
analyzer: &mut Analyzer,
|
||||||
kernel_manager: &mut KernelManager,
|
kernel_manager: &mut KernelManager,
|
||||||
|
core_manager: &mut CoreManager,
|
||||||
router: &mut Router,
|
router: &mut Router,
|
||||||
) -> Result<(), drtioaux::Error> {
|
) -> Result<(), drtioaux::Error> {
|
||||||
// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
|
// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
|
||||||
|
@ -1011,6 +1016,335 @@ fn process_aux_packet(
|
||||||
}
|
}
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtGetLogRequest {
|
||||||
|
destination: _destination,
|
||||||
|
clear,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
let mut data_slice = [0; SAT_PAYLOAD_MAX_SIZE];
|
||||||
|
let meta = core_manager.log_get_slice(&mut data_slice, clear);
|
||||||
|
drtioaux::send(
|
||||||
|
0,
|
||||||
|
&drtioaux::Packet::CoreMgmtGetLogReply {
|
||||||
|
last: meta.status.is_last(),
|
||||||
|
length: meta.len as u16,
|
||||||
|
data: data_slice,
|
||||||
|
},
|
||||||
|
)
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtClearLogRequest {
|
||||||
|
destination: _destination,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
mgmt::clear_log();
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtSetLogLevelRequest {
|
||||||
|
destination: _destination,
|
||||||
|
log_level,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
|
||||||
|
if let Ok(level_filter) = mgmt::byte_to_level_filter(log_level) {
|
||||||
|
info!("Changing log level to {}", level_filter);
|
||||||
|
log::set_max_level(level_filter);
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })
|
||||||
|
} else {
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
|
||||||
|
}
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtSetUartLogLevelRequest {
|
||||||
|
destination: _destination,
|
||||||
|
log_level,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
|
||||||
|
if let Ok(level_filter) = mgmt::byte_to_level_filter(log_level) {
|
||||||
|
info!("Changing UART log level to {}", level_filter);
|
||||||
|
unsafe {
|
||||||
|
logger::BufferLogger::get_logger()
|
||||||
|
.as_ref()
|
||||||
|
.unwrap()
|
||||||
|
.set_uart_log_level(level_filter);
|
||||||
|
}
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })
|
||||||
|
} else {
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
|
||||||
|
}
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtConfigReadRequest {
|
||||||
|
destination: _destination,
|
||||||
|
length,
|
||||||
|
key,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
|
||||||
|
let mut value_slice = [0; SAT_PAYLOAD_MAX_SIZE];
|
||||||
|
|
||||||
|
let key_slice = &key[..length as usize];
|
||||||
|
if !key_slice.is_ascii() {
|
||||||
|
error!("invalid key");
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
|
||||||
|
} else {
|
||||||
|
let key = core::str::from_utf8(key_slice).unwrap();
|
||||||
|
if core_manager.fetch_config_value(key).is_ok() {
|
||||||
|
let meta = core_manager.get_config_value_slice(&mut value_slice);
|
||||||
|
drtioaux::send(
|
||||||
|
0,
|
||||||
|
&drtioaux::Packet::CoreMgmtConfigReadReply {
|
||||||
|
last: meta.status.is_last(),
|
||||||
|
length: meta.len as u16,
|
||||||
|
value: value_slice,
|
||||||
|
},
|
||||||
|
)
|
||||||
|
} else {
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtConfigReadContinue {
|
||||||
|
destination: _destination,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
|
||||||
|
let mut value_slice = [0; SAT_PAYLOAD_MAX_SIZE];
|
||||||
|
let meta = core_manager.get_config_value_slice(&mut value_slice);
|
||||||
|
drtioaux::send(
|
||||||
|
0,
|
||||||
|
&drtioaux::Packet::CoreMgmtConfigReadReply {
|
||||||
|
last: meta.status.is_last(),
|
||||||
|
length: meta.len as u16,
|
||||||
|
value: value_slice,
|
||||||
|
},
|
||||||
|
)
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtConfigWriteRequest {
|
||||||
|
destination: _destination,
|
||||||
|
last,
|
||||||
|
length,
|
||||||
|
data,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
|
||||||
|
core_manager.add_config_data(&data, length as usize);
|
||||||
|
|
||||||
|
let mut succeeded = true;
|
||||||
|
if last {
|
||||||
|
succeeded = core_manager.write_config().is_ok();
|
||||||
|
core_manager.clear_config_data();
|
||||||
|
}
|
||||||
|
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded })
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtConfigRemoveRequest {
|
||||||
|
destination: _destination,
|
||||||
|
length,
|
||||||
|
key,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
|
||||||
|
let key_slice = &key[..length as usize];
|
||||||
|
if !key_slice.is_ascii() {
|
||||||
|
error!("invalid key");
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
|
||||||
|
} else {
|
||||||
|
let key = core::str::from_utf8(key_slice).unwrap();
|
||||||
|
let succeeded = core_manager.remove_config(key).is_ok();
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded })
|
||||||
|
}
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtConfigEraseRequest {
|
||||||
|
destination: _destination,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
|
||||||
|
error!("config erase not supported on zynq device");
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtRebootRequest {
|
||||||
|
destination: _destination,
|
||||||
|
} => {
|
||||||
|
info!("received reboot request");
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })?;
|
||||||
|
info!("reboot imminent");
|
||||||
|
slcr::reboot();
|
||||||
|
|
||||||
|
unreachable!();
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtAllocatorDebugRequest {
|
||||||
|
destination: _destination,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
|
||||||
|
error!("debug allocator not supported on zynq device");
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: false })
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtFlashRequest {
|
||||||
|
destination: _destination,
|
||||||
|
payload_length,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
|
||||||
|
core_manager.allocate_image_buffer(payload_length as usize);
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtFlashAddDataRequest {
|
||||||
|
destination: _destination,
|
||||||
|
last,
|
||||||
|
length,
|
||||||
|
data,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
|
||||||
|
core_manager.add_image_data(&data, length as usize);
|
||||||
|
|
||||||
|
if last {
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtDropLink)
|
||||||
|
} else {
|
||||||
|
drtioaux::send(0, &drtioaux::Packet::CoreMgmtReply { succeeded: true })
|
||||||
|
}
|
||||||
|
}
|
||||||
|
drtioaux::Packet::CoreMgmtDropLinkAck {
|
||||||
|
destination: _destination,
|
||||||
|
} => {
|
||||||
|
forward!(
|
||||||
|
router,
|
||||||
|
_routing_table,
|
||||||
|
_destination,
|
||||||
|
*rank,
|
||||||
|
*self_destination,
|
||||||
|
_repeaters,
|
||||||
|
&packet,
|
||||||
|
timer
|
||||||
|
);
|
||||||
|
|
||||||
|
unsafe {
|
||||||
|
csr::gt_drtio::txenable_write(0);
|
||||||
|
}
|
||||||
|
core_manager.write_image();
|
||||||
|
info!("reboot imminent");
|
||||||
|
slcr::reboot();
|
||||||
|
Ok(())
|
||||||
|
}
|
||||||
|
|
||||||
p => {
|
p => {
|
||||||
warn!("received unexpected aux packet: {:?}", p);
|
warn!("received unexpected aux packet: {:?}", p);
|
||||||
|
@ -1029,6 +1363,7 @@ fn process_aux_packets(
|
||||||
dma_manager: &mut DmaManager,
|
dma_manager: &mut DmaManager,
|
||||||
analyzer: &mut Analyzer,
|
analyzer: &mut Analyzer,
|
||||||
kernel_manager: &mut KernelManager,
|
kernel_manager: &mut KernelManager,
|
||||||
|
core_manager: &mut CoreManager,
|
||||||
router: &mut Router,
|
router: &mut Router,
|
||||||
) {
|
) {
|
||||||
let result = drtioaux::recv(0).and_then(|packet| {
|
let result = drtioaux::recv(0).and_then(|packet| {
|
||||||
|
@ -1044,6 +1379,7 @@ fn process_aux_packets(
|
||||||
dma_manager,
|
dma_manager,
|
||||||
analyzer,
|
analyzer,
|
||||||
kernel_manager,
|
kernel_manager,
|
||||||
|
core_manager,
|
||||||
router,
|
router,
|
||||||
)
|
)
|
||||||
} else {
|
} else {
|
||||||
|
@ -1240,7 +1576,7 @@ pub extern "C" fn main_core0() -> i32 {
|
||||||
#[cfg(has_si549)]
|
#[cfg(has_si549)]
|
||||||
si549::helper_setup(&mut timer, &SI549_SETTINGS).expect("cannot initialize helper Si549");
|
si549::helper_setup(&mut timer, &SI549_SETTINGS).expect("cannot initialize helper Si549");
|
||||||
|
|
||||||
let cfg = match Config::new() {
|
let mut cfg = match Config::new() {
|
||||||
Ok(cfg) => cfg,
|
Ok(cfg) => cfg,
|
||||||
Err(err) => {
|
Err(err) => {
|
||||||
warn!("config initialization failed: {}", err);
|
warn!("config initialization failed: {}", err);
|
||||||
|
@ -1315,6 +1651,7 @@ pub extern "C" fn main_core0() -> i32 {
|
||||||
let mut dma_manager = DmaManager::new();
|
let mut dma_manager = DmaManager::new();
|
||||||
let mut analyzer = Analyzer::new();
|
let mut analyzer = Analyzer::new();
|
||||||
let mut kernel_manager = KernelManager::new(&mut control);
|
let mut kernel_manager = KernelManager::new(&mut control);
|
||||||
|
let mut core_manager = CoreManager::new(&mut cfg);
|
||||||
|
|
||||||
drtioaux::reset(0);
|
drtioaux::reset(0);
|
||||||
drtiosat_reset(false);
|
drtiosat_reset(false);
|
||||||
|
@ -1332,6 +1669,7 @@ pub extern "C" fn main_core0() -> i32 {
|
||||||
&mut dma_manager,
|
&mut dma_manager,
|
||||||
&mut analyzer,
|
&mut analyzer,
|
||||||
&mut kernel_manager,
|
&mut kernel_manager,
|
||||||
|
&mut core_manager,
|
||||||
&mut router,
|
&mut router,
|
||||||
);
|
);
|
||||||
#[allow(unused_mut)]
|
#[allow(unused_mut)]
|
||||||
|
|
|
@ -0,0 +1,149 @@
|
||||||
|
use alloc::vec::Vec;
|
||||||
|
|
||||||
|
use byteorder::{ByteOrder, NativeEndian};
|
||||||
|
use crc::crc32;
|
||||||
|
use io::{ProtoRead, ProtoWrite};
|
||||||
|
use libboard_artiq::{drtioaux_proto::SAT_PAYLOAD_MAX_SIZE,
|
||||||
|
logger::{BufferLogger, LogBufferRef}};
|
||||||
|
use libconfig::Config;
|
||||||
|
use log::{debug, error, info, warn, LevelFilter};
|
||||||
|
|
||||||
|
use crate::routing::{SliceMeta, Sliceable};
|
||||||
|
|
||||||
|
type Result<T> = core::result::Result<T, ()>;
|
||||||
|
|
||||||
|
pub fn byte_to_level_filter(level_byte: u8) -> Result<LevelFilter> {
|
||||||
|
Ok(match level_byte {
|
||||||
|
0 => LevelFilter::Off,
|
||||||
|
1 => LevelFilter::Error,
|
||||||
|
2 => LevelFilter::Warn,
|
||||||
|
3 => LevelFilter::Info,
|
||||||
|
4 => LevelFilter::Debug,
|
||||||
|
5 => LevelFilter::Trace,
|
||||||
|
lv => {
|
||||||
|
error!("unknown log level: {}", lv);
|
||||||
|
return Err(());
|
||||||
|
}
|
||||||
|
})
|
||||||
|
}
|
||||||
|
|
||||||
|
fn get_logger_buffer() -> LogBufferRef<'static> {
|
||||||
|
let logger = unsafe { BufferLogger::get_logger().as_mut().unwrap() };
|
||||||
|
loop {
|
||||||
|
if let Some(buffer_ref) = logger.buffer() {
|
||||||
|
return buffer_ref;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn clear_log() {
|
||||||
|
let mut buffer = get_logger_buffer();
|
||||||
|
buffer.clear();
|
||||||
|
}
|
||||||
|
|
||||||
|
pub struct Manager<'a> {
|
||||||
|
cfg: &'a mut Config,
|
||||||
|
last_log: Sliceable,
|
||||||
|
config_payload: Vec<u8>,
|
||||||
|
last_value: Sliceable,
|
||||||
|
image_payload: Vec<u8>,
|
||||||
|
}
|
||||||
|
|
||||||
|
impl<'a> Manager<'_> {
|
||||||
|
pub fn new(cfg: &mut Config) -> Manager {
|
||||||
|
Manager {
|
||||||
|
cfg: cfg,
|
||||||
|
last_log: Sliceable::new(0, Vec::new()),
|
||||||
|
config_payload: Vec::new(),
|
||||||
|
last_value: Sliceable::new(0, Vec::new()),
|
||||||
|
image_payload: Vec::new(),
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn log_get_slice(&mut self, data_slice: &mut [u8; SAT_PAYLOAD_MAX_SIZE], consume: bool) -> SliceMeta {
|
||||||
|
// Populate buffer if depleted
|
||||||
|
if self.last_log.at_end() {
|
||||||
|
let mut buffer = get_logger_buffer();
|
||||||
|
self.last_log.extend(buffer.extract().as_bytes());
|
||||||
|
if consume {
|
||||||
|
buffer.clear();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
self.last_log.get_slice_satellite(data_slice)
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn fetch_config_value(&mut self, key: &str) -> Result<()> {
|
||||||
|
self.cfg
|
||||||
|
.read(&key)
|
||||||
|
.map(|value| {
|
||||||
|
debug!("got value");
|
||||||
|
|||||||
|
self.last_value = Sliceable::new(0, value)
|
||||||
|
})
|
||||||
|
.map_err(|_| warn!("read error: no such key"))
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn get_config_value_slice(&mut self, data_slice: &mut [u8; SAT_PAYLOAD_MAX_SIZE]) -> SliceMeta {
|
||||||
|
self.last_value.get_slice_satellite(data_slice)
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn add_config_data(&mut self, data: &[u8], data_len: usize) {
|
||||||
|
self.config_payload.write_all(&data[..data_len]).unwrap();
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn clear_config_data(&mut self) {
|
||||||
|
self.config_payload.clear();
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn write_config(&mut self) -> Result<()> {
|
||||||
|
let mut payload = &self.config_payload[..];
|
||||||
|
let key = payload.read_string().map_err(|_err| error!("error on reading key"))?;
|
||||||
|
debug!("write key: {}", key);
|
||||||
|
let value = payload.read_bytes().unwrap();
|
||||||
|
|
||||||
|
self.cfg
|
||||||
|
.write(&key, value)
|
||||||
|
.map(|()| debug!("write success"))
|
||||||
|
.map_err(|err| error!("failed to write: {:?}", err))
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn remove_config(&mut self, key: &str) -> Result<()> {
|
||||||
|
debug!("erase key: {}", key);
|
||||||
|
self.cfg
|
||||||
|
.remove(&key)
|
||||||
|
.map(|()| debug!("erase success"))
|
||||||
|
.map_err(|err| warn!("failed to erase: {:?}", err))
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn allocate_image_buffer(&mut self, image_size: usize) {
|
||||||
|
self.image_payload = Vec::with_capacity(image_size);
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn add_image_data(&mut self, data: &[u8], data_len: usize) {
|
||||||
|
self.image_payload.extend(&data[..data_len]);
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn write_image(&self) {
|
||||||
|
let mut image = self.image_payload.clone();
|
||||||
|
let image_ref = &image[..];
|
||||||
|
let bin_len = image.len() - 4;
|
||||||
|
|
||||||
|
let (image_ref, expected_crc) = {
|
||||||
|
let (image_ref, crc_slice) = image_ref.split_at(bin_len);
|
||||||
|
(image_ref, NativeEndian::read_u32(crc_slice))
|
||||||
|
};
|
||||||
|
|
||||||
|
let actual_crc = crc32::checksum_ieee(image_ref);
|
||||||
|
|
||||||
|
if actual_crc == expected_crc {
|
||||||
|
info!("CRC passed. Writing boot image to SD card...");
|
||||||
|
image.truncate(bin_len);
|
||||||
|
self.cfg.write("boot", image).expect("failed to write boot image");
|
||||||
|
} else {
|
||||||
|
panic!(
|
||||||
|
"CRC failed, images have not been written to flash.\n(actual {:08x}, expected {:08x})",
|
||||||
|
actual_crc, expected_crc
|
||||||
|
);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
|
@ -4,7 +4,7 @@ use core::cmp::min;
|
||||||
#[cfg(has_drtio_routing)]
|
#[cfg(has_drtio_routing)]
|
||||||
use libboard_artiq::pl::csr;
|
use libboard_artiq::pl::csr;
|
||||||
use libboard_artiq::{drtio_routing, drtioaux,
|
use libboard_artiq::{drtio_routing, drtioaux,
|
||||||
drtioaux_proto::{PayloadStatus, MASTER_PAYLOAD_MAX_SIZE}};
|
drtioaux_proto::{PayloadStatus, MASTER_PAYLOAD_MAX_SIZE, SAT_PAYLOAD_MAX_SIZE}};
|
||||||
|
|
||||||
pub struct SliceMeta {
|
pub struct SliceMeta {
|
||||||
pub destination: u8,
|
pub destination: u8,
|
||||||
|
@ -58,6 +58,7 @@ impl Sliceable {
|
||||||
}
|
}
|
||||||
|
|
||||||
get_slice_fn!(get_slice_master, MASTER_PAYLOAD_MAX_SIZE);
|
get_slice_fn!(get_slice_master, MASTER_PAYLOAD_MAX_SIZE);
|
||||||
|
get_slice_fn!(get_slice_satellite, SAT_PAYLOAD_MAX_SIZE);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Packets from downstream (further satellites) are received and routed appropriately.
|
// Packets from downstream (further satellites) are received and routed appropriately.
|
||||||
|
|
Loading…
Reference in New Issue
probably can be removed