Support CoreMgmt over DRTIO on Zynq Devices #323

Merged
sb10q merged 27 commits from occheung/artiq-zynq:drtio-coremgmt into master 2024-11-19 18:55:03 +08:00
2 changed files with 9 additions and 12 deletions
Showing only changes of commit 47d418c69e - Show all commits

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@ -135,7 +135,7 @@ async fn read_key(stream: &mut TcpStream) -> Result<String> {
#[cfg(has_drtio)] #[cfg(has_drtio)]
mod remote_coremgmt { mod remote_coremgmt {
use core_io::Read; use core_io::Read;
use io::{Cursor, ProtoWrite}; use io::ProtoWrite;
use libboard_artiq::{drtioaux_async, use libboard_artiq::{drtioaux_async,
drtioaux_proto::{Packet, MASTER_PAYLOAD_MAX_SIZE}}; drtioaux_proto::{Packet, MASTER_PAYLOAD_MAX_SIZE}};
@ -427,7 +427,7 @@ mod remote_coremgmt {
value: Vec<u8>, value: Vec<u8>,
_restart_idle: &Rc<Semaphore>, _restart_idle: &Rc<Semaphore>,
) -> Result<()> { ) -> Result<()> {
let mut message = Cursor::new(Vec::with_capacity(key.len() + value.len() + 4 * 2)); let mut message = Vec::with_capacity(key.len() + value.len() + 4 * 2);
message.write_string(key).unwrap(); message.write_string(key).unwrap();
message.write_bytes(&value).unwrap(); message.write_bytes(&value).unwrap();
@ -436,7 +436,7 @@ mod remote_coremgmt {
aux_mutex, aux_mutex,
routing_table, routing_table,
timer, timer,
message.get_ref(), &message,
|slice, status, len: usize| Packet::CoreMgmtConfigWriteRequest { |slice, status, len: usize| Packet::CoreMgmtConfigWriteRequest {
destination: destination, destination: destination,
last: status.is_last(), last: status.is_last(),

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@ -48,7 +48,7 @@ pub fn clear_log() {
pub struct Manager<'a> { pub struct Manager<'a> {
cfg: &'a mut Config, cfg: &'a mut Config,
last_log: Sliceable, last_log: Sliceable,
config_payload: Cursor<Vec<u8>>, config_payload: Vec<u8>,
last_value: Sliceable, last_value: Sliceable,
image_payload: Vec<u8>, image_payload: Vec<u8>,
} }
@ -58,7 +58,7 @@ impl<'a> Manager<'_> {
Manager { Manager {
cfg: cfg, cfg: cfg,
last_log: Sliceable::new(0, Vec::new()), last_log: Sliceable::new(0, Vec::new()),
config_payload: Cursor::new(Vec::new()), config_payload: Vec::new(),
last_value: Sliceable::new(0, Vec::new()), last_value: Sliceable::new(0, Vec::new()),
image_payload: Vec::new(), image_payload: Vec::new(),
} }
@ -92,17 +92,14 @@ impl<'a> Manager<'_> {
} }
pub fn clear_config_data(&mut self) { pub fn clear_config_data(&mut self) {
self.config_payload.get_mut().clear(); self.config_payload.clear();
self.config_payload.set_position(0);
} }
pub fn write_config(&mut self) -> Result<()> { pub fn write_config(&mut self) -> Result<()> {
let key = self let mut payload = &self.config_payload[..];
.config_payload let key = payload.read_string().map_err(|_err| error!("error on reading key"))?;
.read_string()
.map_err(|_err| error!("error on reading key"))?;
debug!("write key: {}", key); debug!("write key: {}", key);
let value = self.config_payload.read_bytes().unwrap(); let value = payload.read_bytes().unwrap();
self.cfg self.cfg
.write(&key, value) .write(&key, value)