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DDMTD: replace FD with ISERDESE2 #292

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sb10q merged 2 commits from morgan/artiq-zynq:DDMTD into master 2024-04-29 13:03:30 +08:00
Conversation 0 Commits 2 Files Changed 2 +39 -13
2 changed files with 39 additions and 13 deletions
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50
src/gateware/ddmtd.py
View File

@ -10,18 +10,44 @@ class DDMTDSampler(Module):
# # # # # #
ref_beating_FF = Signal() ref_clk = Signal()
main_beating_FF = Signal() self.specials +=[
self.specials += [ # ISERDESE2 can only be driven from fabric via IDELAYE2 (see UG471)
# Two back to back FFs are used to prevent metastability Instance("IDELAYE2",
Instance("FD", i_C=ClockSignal("helper"), p_DELAY_SRC="DATAIN",
i_D=cd_ref.clk, o_Q=ref_beating_FF), p_HIGH_PERFORMANCE_MODE="TRUE",
Instance("FD", i_C=ClockSignal("helper"), p_REFCLK_FREQUENCY=208.3, # REFCLK frequency from IDELAYCTRL
i_D=ref_beating_FF, o_Q=self.ref_beating), p_IDELAY_VALUE=0,
Instance("FD", i_C=ClockSignal("helper"),
i_D=main_clk_se, o_Q=main_beating_FF), i_DATAIN=cd_ref.clk,
Instance("FD", i_C=ClockSignal("helper"),
i_D=main_beating_FF, o_Q=self.main_beating) o_DATAOUT=ref_clk
),
Instance("ISERDESE2",
p_IOBDELAY="IFD", # use DDLY as input
p_DATA_RATE="SDR",
p_DATA_WIDTH=2, # min is 2
p_NUM_CE=1,
i_DDLY=ref_clk,
i_CE1=1,
i_CLK=ClockSignal("helper"),
i_CLKDIV=ClockSignal("helper"),
o_Q1=self.ref_beating
),
Instance("ISERDESE2",
p_DATA_RATE="SDR",
p_DATA_WIDTH=2, # min is 2
p_NUM_CE=1,
i_D=main_clk_se,
i_CE1=1,
i_CLK=ClockSignal("helper"),
i_CLKDIV=ClockSignal("helper"),
o_Q1=self.main_beating,
),
] ]

2
src/libboard_artiq/src/si549.rs
View File

@ -356,7 +356,7 @@ pub mod wrpll {
use super::*; use super::*;
#[cfg(wrpll_ref_clk = "GT_CDR")] #[cfg(wrpll_ref_clk = "GT_CDR")]
static mut TAG_OFFSET: u32 = 19050; static mut TAG_OFFSET: u32 = 8382;
#[cfg(wrpll_ref_clk = "SMA_CLKIN")] #[cfg(wrpll_ref_clk = "SMA_CLKIN")]
static mut TAG_OFFSET: u32 = 0; static mut TAG_OFFSET: u32 = 0;
static mut REF_TAG: u32 = 0; static mut REF_TAG: u32 = 0;