From e3a4c139447d4529f726d49b41bba7b6fbe44a0b Mon Sep 17 00:00:00 2001 From: linuswck Date: Mon, 6 Nov 2023 12:16:39 +0800 Subject: [PATCH 1/4] zynq_clocking: expose mmcm_locked for SYSCRG - mmcm_locked -> self.mmcm_locked --- src/gateware/zynq_clocking.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index b85c365..d94b1bc 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -88,7 +88,7 @@ class SYSCRG(Module, AutoCSR): else: self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw) - mmcm_locked = Signal() + self.mmcm_locked = Signal() mmcm_sys = Signal() mmcm_sys4x = Signal() mmcm_sys5x = Signal() @@ -96,7 +96,7 @@ class SYSCRG(Module, AutoCSR): mmcm_fb_clk = Signal() self.specials += [ Instance("MMCME2_ADV", - p_STARTUP_WAIT="FALSE", o_LOCKED=mmcm_locked, + p_STARTUP_WAIT="FALSE", o_LOCKED=self.mmcm_locked, p_BANDWIDTH="HIGH", p_REF_JITTER1=0.001, p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk, @@ -125,8 +125,8 @@ class SYSCRG(Module, AutoCSR): Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=mmcm_sys4x, o_O=self.cd_sys4x.clk), Instance("BUFG", i_I=mmcm_clk208, o_O=self.cd_clk200.clk), - AsyncResetSynchronizer(self.cd_sys, ~mmcm_locked), - AsyncResetSynchronizer(self.cd_clk200, ~mmcm_locked), + AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked), + AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked), ] reset_counter = Signal(4, reset=15) -- 2.42.0 From d507b6f60ff275d03417e4d23f2b97d0f76163dc Mon Sep 17 00:00:00 2001 From: linuswck Date: Mon, 6 Nov 2023 12:24:44 +0800 Subject: [PATCH 2/4] zynq_clocking: add ext_async_rst to AsyncRstSYNCR --- src/gateware/zynq_clocking.py | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index d94b1bc..553a43f 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -65,7 +65,7 @@ class ClockSwitchFSM(Module): class SYSCRG(Module, AutoCSR): - def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6): + def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6, ext_async_rst=None): # assumes bootstrap clock is same freq as main and sys output self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -125,10 +125,19 @@ class SYSCRG(Module, AutoCSR): Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=mmcm_sys4x, o_O=self.cd_sys4x.clk), Instance("BUFG", i_I=mmcm_clk208, o_O=self.cd_clk200.clk), - AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked), - AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked), ] + if ext_async_rst is not None: + self.specials += [ + AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked | ext_async_rst), + AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked | ext_async_rst), + ] + else: + self.specials += [ + AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked), + AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked), + ] + reset_counter = Signal(4, reset=15) ic_reset = Signal(reset=1) self.sync.clk200 += \ -- 2.42.0 From 4a2d9dc59723f2e127fecec55b84660c8fe62301 Mon Sep 17 00:00:00 2001 From: linuswck Date: Tue, 7 Nov 2023 15:40:50 +0800 Subject: [PATCH 3/4] zynq_clocking: Allow ext signal to set cur_clk csr - for example, current_clock csr can be connected to tx_init.done --- src/gateware/zynq_clocking.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gateware/zynq_clocking.py b/src/gateware/zynq_clocking.py index 553a43f..5a7e7c3 100644 --- a/src/gateware/zynq_clocking.py +++ b/src/gateware/zynq_clocking.py @@ -65,7 +65,7 @@ class ClockSwitchFSM(Module): class SYSCRG(Module, AutoCSR): - def __init__(self, platform, ps7, main_clk, clk_sw=None, freq=125e6, ext_async_rst=None): + def __init__(self, platform, ps7, main_clk, clk_sw=None, clk_sw_status=None, freq=125e6, ext_async_rst=None, ): # assumes bootstrap clock is same freq as main and sys output self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -148,4 +148,7 @@ class SYSCRG(Module, AutoCSR): ) self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset) - self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw) + if clk_sw_status is None: + self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw) + else: + self.comb += self.current_clock.status.eq(clk_sw_status) -- 2.42.0 From 0e3987c8872feed311c97654c44e2b08afaf9e12 Mon Sep 17 00:00:00 2001 From: linuswck Date: Mon, 6 Nov 2023 16:48:37 +0800 Subject: [PATCH 4/4] kasli_soc & zc706: Fix GTX Clock Path during INIT --- src/gateware/kasli_soc.py | 18 ++++++++++++++++-- src/gateware/zc706.py | 16 ++++++++++++++-- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 4bcb8ed..25e9c04 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -237,12 +237,16 @@ class GenericMaster(SoCCore): gtx0 = self.gt_drtio.gtxs[0] self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) + ext_async_rst = Signal() + self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, txout_buf, - clk_sw=gtx0.tx_init.done) + clk_sw=self.gt_drtio.stable_clkin.storage, + clk_sw_status=gtx0.tx_init.done, + ext_async_rst=ext_async_rst) self.csr_devices.append("sys_crg") self.crg = self.ps7 # HACK for eem_7series to find the clock self.crg.cd_sys = self.sys_crg.cd_sys @@ -250,6 +254,9 @@ class GenericMaster(SoCCore): self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) fix_serdes_timing_path(platform) + self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done) + self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap") + self.config["HAS_SI5324"] = None self.config["SI5324_SOFT_RESET"] = None @@ -419,12 +426,16 @@ class GenericSatellite(SoCCore): gtx0 = self.gt_drtio.gtxs[0] self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) + ext_async_rst = Signal() + self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq) self.submodules.sys_crg = zynq_clocking.SYSCRG( self.platform, self.ps7, txout_buf, - clk_sw=gtx0.tx_init.done) + clk_sw=self.gt_drtio.stable_clkin.storage, + clk_sw_status=gtx0.tx_init.done, + ext_async_rst=ext_async_rst) platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") @@ -433,6 +444,9 @@ class GenericSatellite(SoCCore): fix_serdes_timing_path(platform) + self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done) + self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap") + self.rtio_channels = [] has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"]) if has_grabber: diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index f9556e6..92c9208 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -226,6 +226,7 @@ class _MasterBase(SoCCore): self.csr_devices.append("gt_drtio") self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3) + ext_async_rst = Signal() txout_buf = Signal() gtx0 = self.gt_drtio.gtxs[0] self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) @@ -234,12 +235,17 @@ class _MasterBase(SoCCore): self.platform, self.ps7, txout_buf, - clk_sw=gtx0.tx_init.done, + clk_sw=self.gt_drtio.stable_clkin.storage, + clk_sw_status=gtx0.tx_init.done, + ext_async_rst=ext_async_rst, freq=clk_freq) platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") + self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done) + self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap") + drtio_csr_group = [] drtioaux_csr_group = [] drtioaux_memory_group = [] @@ -361,6 +367,7 @@ class _SatelliteBase(SoCCore): clk_freq=clk_freq) self.csr_devices.append("gt_drtio") + ext_async_rst = Signal() txout_buf = Signal() txout_buf.attr.add("keep") gtx0 = self.gt_drtio.gtxs[0] @@ -373,12 +380,17 @@ class _SatelliteBase(SoCCore): self.platform, self.ps7, txout_buf, - clk_sw=gtx0.tx_init.done, + clk_sw=self.gt_drtio.stable_clkin.storage, + clk_sw_status=gtx0.tx_init.done, + ext_async_rst=ext_async_rst, freq=clk_freq) platform.add_false_path_constraints( self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.csr_devices.append("sys_crg") + self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done) + self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap") + drtioaux_csr_group = [] drtioaux_memory_group = [] drtiorep_csr_group = [] -- 2.42.0