Add grabber module to release-7 #271

Merged
sb10q merged 1 commits from esavkin/artiq-zynq:264-grabber-backport into release-7 2023-10-19 14:24:03 +08:00
Owner

Waits for customer test.

Closes #264

Waits for customer test. Closes #264
esavkin force-pushed 264-grabber-backport from 2d88a44e1c to f56959aed7 2023-10-17 16:58:42 +08:00 Compare
esavkin changed title from WIP: Add grabber module to release-7 to Add grabber module to release-7 2023-10-18 11:18:05 +08:00
esavkin changed title from Add grabber module to release-7 to WIP: Add grabber module to release-7 2023-10-18 11:18:32 +08:00
esavkin changed title from WIP: Add grabber module to release-7 to Add grabber module to release-7 2023-10-18 13:07:01 +08:00
Author
Owner

Customer confirmed that this version works ok

Customer confirmed that this version works ok
sb10q reviewed 2023-10-18 14:03:44 +08:00
@ -142,6 +143,7 @@ class GenericStandalone(SoCCore):
self.ps7.cd_sys.clk,
self.rtio_crg.cd_rtio.clk)
fix_serdes_timing_path(platform)
self.config["CLOCK_FREQUENCY"] = int(rtio_clk_freq)
Owner

Looks incorrect. On softcore platforms this is set by MiSoC which does not know anything about RTIO, so this has to be the system clock frequency.

Looks incorrect. On softcore platforms this is set by MiSoC which does not know anything about RTIO, so this has to be the system clock frequency.
Author
Owner

Is that that is defined by such line in GenericMaster?

sys_clk_freq = 125e6
Is that that is defined by such line in GenericMaster? ``` sys_clk_freq = 125e6 ```
Owner

I'm just talking about the value of self.config["CLOCK_FREQUENCY"] here.

I'm just talking about the value of ``self.config["CLOCK_FREQUENCY"]`` here.
Author
Owner

I'm just talking about the value of self.config["CLOCK_FREQUENCY"] here.

Yes, I mean so this has to be the system clock frequency refers to sys_clk_freq = 125e6 ? Or it is another variable generated somewhere else?

> I'm just talking about the value of ``self.config["CLOCK_FREQUENCY"]`` here. Yes, I mean `so this has to be the system clock frequency` refers to `sys_clk_freq = 125e6` ? Or it is another variable generated somewhere else?
Owner

sys_clk_freq is the one that should be used, as grabber clock is based off the system clock domain (deserializer_7series.py#L22) , and as RTIO clock (theoretically) can be of a different frequency.

And yes it's defined right there. Migen-axi doesn't redefine the sys clock.

``sys_clk_freq`` is the one that should be used, as grabber clock is based off the system clock domain ([deserializer_7series.py#L22](https://github.com/m-labs/artiq/blob/release-7/artiq/gateware/grabber/deserializer_7series.py#L22)) , and as RTIO clock (theoretically) can be of a different frequency. And yes it's defined right there. Migen-axi doesn't redefine the sys clock.
esavkin force-pushed 264-grabber-backport from f56959aed7 to 9b76896edd 2023-10-18 15:02:07 +08:00 Compare
sb10q merged commit 9b76896edd into release-7 2023-10-19 14:24:03 +08:00
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Reference: M-Labs/artiq-zynq#271
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