Add grabber module to release-7 #271
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Reference: M-Labs/artiq-zynq#271
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Delete Branch "esavkin/artiq-zynq:264-grabber-backport"
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Waits for customer test.
Closes #264
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WIP: Add grabber module to release-7to Add grabber module to release-7Add grabber module to release-7to WIP: Add grabber module to release-7WIP: Add grabber module to release-7to Add grabber module to release-7Customer confirmed that this version works ok
@ -142,6 +143,7 @@ class GenericStandalone(SoCCore):
self.ps7.cd_sys.clk,
self.rtio_crg.cd_rtio.clk)
fix_serdes_timing_path(platform)
self.config["CLOCK_FREQUENCY"] = int(rtio_clk_freq)
Looks incorrect. On softcore platforms this is set by MiSoC which does not know anything about RTIO, so this has to be the system clock frequency.
Is that that is defined by such line in GenericMaster?
I'm just talking about the value of
self.config["CLOCK_FREQUENCY"]
here.Yes, I mean
so this has to be the system clock frequency
refers tosys_clk_freq = 125e6
? Or it is another variable generated somewhere else?sys_clk_freq
is the one that should be used, as grabber clock is based off the system clock domain (deserializer_7series.py#L22) , and as RTIO clock (theoretically) can be of a different frequency.And yes it's defined right there. Migen-axi doesn't redefine the sys clock.
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