fix 100mhz PLL bypass support #265
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Reference: M-Labs/artiq-zynq#265
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Delete Branch "mwojcik/artiq-zynq:100mhz_support"
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This should fix issues @ljstephenson has. Bypassing the PLL with GTX/GTP didn't work because of mismatched frequencies of bootstrap clock (125MHz, default for RTIO) and the external clock.
Tested with both Kasli-SoC and ZC706, with an external 100MHz clock source and
ext0_bypass
in the config:Do note that for ZC706 the variants with
_100mhz
suffix need to be used, which are now exposed in the flake. Seems like standalone is not affected by the frequency change, so that remains untouched.For Kasli-SoC,
rtio_frequency
needs to be defined in the JSON file.cb10903899
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