From aa2009d49e268d94b5abdae9f6623bd58aa2bce1 Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 7 Sep 2023 16:47:54 +0800 Subject: [PATCH 1/3] replace rustc_cfg[ ] & change write_rustc_cfg_file --- src/gateware/zc706.py | 53 +++++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 27 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index aaad33a..e770633 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -127,7 +127,6 @@ def prepare_zc706_platform(platform): class ZC706(SoCCore): def __init__(self, acpki=False): self.acpki = acpki - self.rustc_cfg = dict() platform = zc706.Platform() prepare_zc706_platform(platform) @@ -154,9 +153,9 @@ class ZC706(SoCCore): p_CLKSWING_CFG=3), Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf) ] - self.rustc_cfg["has_si5324"] = None - self.rustc_cfg["si5324_as_synthesizer"] = None - self.rustc_cfg["si5324_soft_reset"] = None + self.config["HAS_SI5324"] = None + self.config["SI5324_AS_SYNTHESIZER"] = None + self.config["SI5324_SOFT_RESET"] = None self.submodules.bootstrap = CLK200BootstrapClock(platform) self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, cdr_clk_buf) @@ -170,14 +169,14 @@ class ZC706(SoCCore): self.csr_devices.append("rtio_core") if self.acpki: - self.rustc_cfg["ki_impl"] = "acp" + self.config["KI_IMPL"] = "acp" self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, bus=self.ps7.s_axi_acp, user=self.ps7.s_axi_acp_user, evento=self.ps7.event.o) self.csr_devices.append("rtio") else: - self.rustc_cfg["ki_impl"] = "csr" + self.config["KI_IMPL"] = "csr" self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True) self.csr_devices.append("rtio") @@ -200,7 +199,6 @@ class ZC706(SoCCore): class _MasterBase(SoCCore): def __init__(self, acpki=False, drtio100mhz=False): self.acpki = acpki - self.rustc_cfg = dict() clk_freq = 100e6 if drtio100mhz else 125e6 @@ -271,18 +269,18 @@ class _MasterBase(SoCCore): memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), mem_size) self.axi2csr.register_port(coreaux.get_rx_port(), mem_size) self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2) - self.rustc_cfg["has_drtio"] = None - self.rustc_cfg["has_drtio_routing"] = None + self.config["HAS_DRTIO"] = None + self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtio", drtio_csr_group) self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) - self.rustc_cfg["rtio_frequency"] = str(self.gt_drtio.rtio_clk_freq/1e6) + self.config["RTIO_FREQUENCY"] = str(self.gt_drtio.rtio_clk_freq/1e6) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) self.csr_devices.append("si5324_rst_n") - self.rustc_cfg["has_si5324"] = None - self.rustc_cfg["si5324_as_synthesizer"] = None + self.config["HAS_SI5324"] = None + self.config["SI5324_AS_SYNTHESIZER"] = None # Constrain TX & RX timing for the first transceiver channel # (First channel acts as master for phase alignment for all channels' TX) @@ -302,14 +300,14 @@ class _MasterBase(SoCCore): self.csr_devices.append("rtio_core") if self.acpki: - self.rustc_cfg["ki_impl"] = "acp" + self.config["KI_IMPL"] = "acp" self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, bus=self.ps7.s_axi_acp, user=self.ps7.s_axi_acp_user, evento=self.ps7.event.o) self.csr_devices.append("rtio") else: - self.rustc_cfg["ki_impl"] = "csr" + self.config["KI_IMPL"] = "csr" self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True) self.csr_devices.append("rtio") @@ -336,7 +334,6 @@ class _MasterBase(SoCCore): class _SatelliteBase(SoCCore): def __init__(self, acpki=False, drtio100mhz=False): self.acpki = acpki - self.rustc_cfg = dict() clk_freq = 100e6 if drtio100mhz else 125e6 @@ -425,13 +422,13 @@ class _SatelliteBase(SoCCore): # and registered in PS interface # manually, because software refers to rx/tx by halves of entire memory block, not names self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2) - self.rustc_cfg["has_drtio"] = None - self.rustc_cfg["has_drtio_routing"] = None + self.config["HAS_DRTIO"] = None + self.config["HAS_DRTIO_ROUTING"] = None self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_csr_group("drtiorep", drtiorep_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) - self.rustc_cfg["rtio_frequency"] = str(self.gt_drtio.rtio_clk_freq/1e6) + self.config["RTIO_FREQUENCY"] = str(self.gt_drtio.rtio_clk_freq/1e6) # Si5324 Phaser self.submodules.siphaser = SiPhaser7Series( @@ -444,8 +441,7 @@ class _SatelliteBase(SoCCore): self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) self.csr_devices.append("si5324_rst_n") - self.rustc_cfg["has_si5324"] = None - self.rustc_cfg["has_siphaser"] = None + self.config["HAS_SI5324"] = None rtio_clk_period = 1e9/self.gt_drtio.rtio_clk_freq # Constrain TX & RX timing for the first transceiver channel @@ -465,14 +461,14 @@ class _SatelliteBase(SoCCore): self.csr_devices.append("rtio_moninj") if self.acpki: - self.rustc_cfg["ki_impl"] = "acp" + self.config["KI_IMPL"] = "acp" self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc, bus=self.ps7.s_axi_acp, user=self.ps7.s_axi_acp_user, evento=self.ps7.event.o) self.csr_devices.append("rtio") else: - self.rustc_cfg["ki_impl"] = "csr" + self.config["KI_IMPL"] = "csr" self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True) self.csr_devices.append("rtio") @@ -690,11 +686,14 @@ def write_mem_file(soc, filename): def write_rustc_cfg_file(soc, filename): with open(filename, "w") as f: - for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)): - if v is None: - f.write("{}\n".format(k)) - else: - f.write("{}=\"{}\"\n".format(k, v)) + for name, origin, busword, obj in soc.get_csr_regions(): + f.write("has_{}\n".format(name.lower())) + for name, value in soc.get_constants(): + if name.upper().startswith("CONFIG_"): + if value is None: + f.write("{}\n".format(name.lower()[7:])) + else: + f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value))) def main(): -- 2.47.2 From 4716d1a4c5f2a3f3d183e95337cef0b81f181ac3 Mon Sep 17 00:00:00 2001 From: morgan Date: Mon, 11 Sep 2023 11:15:55 +0800 Subject: [PATCH 2/3] consolidate all `write..file()` into `config.py` --- src/gateware/config.py | 22 ++++++++++++++++++++++ src/gateware/kasli_soc.py | 28 +--------------------------- src/gateware/zc706.py | 27 +-------------------------- 3 files changed, 24 insertions(+), 53 deletions(-) create mode 100644 src/gateware/config.py diff --git a/src/gateware/config.py b/src/gateware/config.py new file mode 100644 index 0000000..10150df --- /dev/null +++ b/src/gateware/config.py @@ -0,0 +1,22 @@ +from misoc.integration import cpu_interface + +def write_csr_file(soc, filename): + with open(filename, "w") as f: + f.write(cpu_interface.get_csr_rust( + soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants())) + +def write_mem_file(soc, filename): + with open(filename, "w") as f: + f.write(cpu_interface.get_mem_rust( + soc.get_memory_regions(), soc.get_memory_groups(), None)) + +def write_rustc_cfg_file(soc, filename): + with open(filename, "w") as f: + for name, origin, busword, obj in soc.get_csr_regions(): + f.write("has_{}\n".format(name.lower())) + for name, value in soc.get_constants(): + if name.upper().startswith("CONFIG_"): + if value is None: + f.write("{}\n".format(name.lower()[7:])) + else: + f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value))) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index 3cce229..2a3c0cb 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -11,7 +11,6 @@ from migen_axi.integration.soc_core import SoCCore from migen_axi.platforms import kasli_soc from misoc.interconnect.csr import * from misoc.cores import virtual_leds -from misoc.integration import cpu_interface from artiq.coredevice import jsondesc from artiq.gateware import rtio, eem_7series @@ -27,7 +26,7 @@ import analyzer import acpki import drtio_aux_controller import zynq_clocking - +from config import write_csr_file, write_mem_file, write_rustc_cfg_file eem_iostandard_dict = { 0: "LVDS_25", @@ -484,31 +483,6 @@ class GenericSatellite(SoCCore): self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready) for i, channel in enumerate(self.gt_drtio.channels)] - -def write_mem_file(soc, filename): - with open(filename, "w") as f: - f.write(cpu_interface.get_mem_rust( - soc.get_memory_regions(), soc.get_memory_groups(), None)) - - -def write_csr_file(soc, filename): - with open(filename, "w") as f: - f.write(cpu_interface.get_csr_rust( - soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants())) - - -def write_rustc_cfg_file(soc, filename): - with open(filename, "w") as f: - for name, origin, busword, obj in soc.get_csr_regions(): - f.write("has_{}\n".format(name.lower())) - for name, value in soc.get_constants(): - if name.upper().startswith("CONFIG_"): - if value is None: - f.write("{}\n".format(name.lower()[7:])) - else: - f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value))) - - def main(): parser = argparse.ArgumentParser( description="ARTIQ device binary builder for generic Kasli-SoC systems") diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index e770633..6ae46b4 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -10,7 +10,6 @@ from migen.genlib.cdc import MultiReg from migen_axi.integration.soc_core import SoCCore from migen_axi.platforms import zc706 from misoc.interconnect.csr import * -from misoc.integration import cpu_interface from misoc.cores import gpio from artiq.gateware import rtio, nist_clock, nist_qc2 @@ -26,7 +25,7 @@ import analyzer import acpki import drtio_aux_controller import zynq_clocking - +from config import write_csr_file, write_mem_file, write_rustc_cfg_file class SMAClkinForward(Module): def __init__(self, platform): @@ -672,30 +671,6 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO): VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite, NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]} - -def write_csr_file(soc, filename): - with open(filename, "w") as f: - f.write(cpu_interface.get_csr_rust( - soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants())) - -def write_mem_file(soc, filename): - with open(filename, "w") as f: - f.write(cpu_interface.get_mem_rust( - soc.get_memory_regions(), soc.get_memory_groups(), None)) - - -def write_rustc_cfg_file(soc, filename): - with open(filename, "w") as f: - for name, origin, busword, obj in soc.get_csr_regions(): - f.write("has_{}\n".format(name.lower())) - for name, value in soc.get_constants(): - if name.upper().startswith("CONFIG_"): - if value is None: - f.write("{}\n".format(name.lower()[7:])) - else: - f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value))) - - def main(): parser = argparse.ArgumentParser( description="ARTIQ port to the ZC706 Zynq development kit") -- 2.47.2 From 38078574230aa6e45046c321e59aee6454551189 Mon Sep 17 00:00:00 2001 From: morgan Date: Mon, 11 Sep 2023 11:46:17 +0800 Subject: [PATCH 3/3] refactor `write_rustc_cfg_file()` --- src/gateware/config.py | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/gateware/config.py b/src/gateware/config.py index 10150df..78f97a4 100644 --- a/src/gateware/config.py +++ b/src/gateware/config.py @@ -12,11 +12,5 @@ def write_mem_file(soc, filename): def write_rustc_cfg_file(soc, filename): with open(filename, "w") as f: - for name, origin, busword, obj in soc.get_csr_regions(): - f.write("has_{}\n".format(name.lower())) - for name, value in soc.get_constants(): - if name.upper().startswith("CONFIG_"): - if value is None: - f.write("{}\n".format(name.lower()[7:])) - else: - f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value))) + f.write(cpu_interface.get_rust_cfg( + soc.get_csr_regions(), soc.get_constants())) -- 2.47.2