M-Labs
/
artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests Releases Wiki Activity

fix #228 and initialize io_dir setting at io_expander.rs #257

Merged
sb10q merged 2 commits from morgan/artiq-zynq:bugfix_pinswap into release-7 2023-09-04 15:50:45 +08:00
Conversation 1 Commits 2 Files Changed 4 +29 -12
4 changed files with 29 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/gateware/kasli_soc.py
View File

@ -123,6 +123,8 @@ class GenericStandalone(SoCCore):
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
self.config["hw_rev"] = description["hw_rev"]
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
@ -209,6 +211,8 @@ class GenericMaster(SoCCore):
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
self.config["hw_rev"] = description["hw_rev"]
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
@ -334,6 +338,8 @@ class GenericSatellite(SoCCore):
ident = "acpki_" + ident ident = "acpki_" + ident
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
self.config["hw_rev"] = description["hw_rev"]
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")

23
src/libboard_artiq/src/io_expander.rs
View File

@ -10,6 +10,25 @@ struct Registers {
gpiob: u8, // Output Port 1 gpiob: u8, // Output Port 1
} }
//IO expanders pins
const IODIR_OUT_SFP_TX_DISABLE: u8 = 0x02;
const IODIR_OUT_SFP_LED: u8 = 0x40;
#[cfg(hw_rev = "v1.0")]
const IODIR_OUT_SFP0_LED: u8 = 0x40;
#[cfg(hw_rev = "v1.1")]
const IODIR_OUT_SFP0_LED: u8 = 0x80;
//IO expander port direction
const IODIR0: [u8; 2] = [
0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP0_LED,
0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP_LED,
];
const IODIR1: [u8; 2] = [
0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP_LED,
0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP_LED,
];
pub struct IoExpander { pub struct IoExpander {
address: u8, address: u8,
iodir: [u8; 2], iodir: [u8; 2],
@ -25,7 +44,7 @@ impl IoExpander {
let mut io_expander = match index { let mut io_expander = match index {
0 => IoExpander { 0 => IoExpander {
address: 0x40, address: 0x40,
iodir: [0xff; 2], iodir: IODIR0,
out_current: [0; 2], out_current: [0; 2],
out_target: [0; 2], out_target: [0; 2],
registers: Registers { registers: Registers {
@ -37,7 +56,7 @@ impl IoExpander {
}, },
1 => IoExpander { 1 => IoExpander {
address: 0x42, address: 0x42,
iodir: [0xff; 2], iodir: IODIR1,
out_current: [0; 2], out_current: [0; 2],
out_target: [0; 2], out_target: [0; 2],
registers: Registers { registers: Registers {

6
src/runtime/src/main.rs
View File

@ -128,11 +128,7 @@ pub fn main_core0() {
io_expander1 io_expander1
.init(i2c_bus) .init(i2c_bus)
.expect("I2C I/O expander #1 initialization failed"); .expect("I2C I/O expander #1 initialization failed");
// Actively drive TX_DISABLE to false on SFP0..3 // Drive TX_DISABLE to false on SFP0..3
io_expander0.set_oe(i2c_bus, 0, 1 << 1).unwrap();
io_expander1.set_oe(i2c_bus, 0, 1 << 1).unwrap();
io_expander0.set_oe(i2c_bus, 1, 1 << 1).unwrap();
io_expander1.set_oe(i2c_bus, 1, 1 << 1).unwrap();
io_expander0.set(0, 1, false); io_expander0.set(0, 1, false);
io_expander1.set(0, 1, false); io_expander1.set(0, 1, false);
io_expander0.set(1, 1, false); io_expander0.set(1, 1, false);

6
src/satman/src/main.rs
View File

@ -483,11 +483,7 @@ pub extern fn main_core0() -> i32 {
io_expander1 io_expander1
.init(&mut i2c) .init(&mut i2c)
.expect("I2C I/O expander #1 initialization failed"); .expect("I2C I/O expander #1 initialization failed");
// Actively drive TX_DISABLE to false on SFP0..3 // Drive TX_DISABLE to false on SFP0..3
morgan marked this conversation as resolved Outdated
sb10q commented 2023-09-04 14:29:39 +08:00
Outdated
Review
Copy Link

"Actively" comment becomes misleading since the code it refers to no longer touches OE.

"Actively" comment becomes misleading since the code it refers to no longer touches OE.
io_expander0.set_oe(&mut i2c, 0, 1 << 1).unwrap();
io_expander1.set_oe(&mut i2c, 0, 1 << 1).unwrap();
io_expander0.set_oe(&mut i2c, 1, 1 << 1).unwrap();
io_expander1.set_oe(&mut i2c, 1, 1 << 1).unwrap();
io_expander0.set(0, 1, false); io_expander0.set(0, 1, false);
io_expander1.set(0, 1, false); io_expander1.set(0, 1, false);
io_expander0.set(1, 1, false); io_expander0.set(1, 1, false);