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Fix kasli_soc-demo compilation error with cfg #250

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sb10q merged 2 commits from morgan/artiq-zynq:bugfix into master 2023-08-30 15:33:45 +08:00
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src/gateware/kasli_soc.py
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@ -310,6 +310,7 @@ class GenericMaster(SoCCore):
self.add_csr_group("grabber", self.grabber_csr_group) self.add_csr_group("grabber", self.grabber_csr_group)
self.rustc_cfg["has_virtual_leds"] = None
self.submodules.virtual_leds = virtual_leds.VirtualLeds() self.submodules.virtual_leds = virtual_leds.VirtualLeds()
self.csr_devices.append("virtual_leds") self.csr_devices.append("virtual_leds")
@ -482,6 +483,7 @@ class GenericSatellite(SoCCore):
self.add_csr_group("grabber", self.grabber_csr_group) self.add_csr_group("grabber", self.grabber_csr_group)
# no RTIO CRG here # no RTIO CRG here
self.rustc_cfg["has_virtual_leds"] = None
sb10q commented 2023-08-29 11:26:03 +08:00
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IIRC misoc does that by default for all CSR cores and those lines are not necessary?

IIRC misoc does that by default for all CSR cores and those lines are not necessary?
morgan commented 2023-08-29 11:32:39 +08:00
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Running python src/gateware/kasli_soc.py -r build/pl.rs -c build/rustc-cfg -m build/mem.rs kasli-soc-satellite.json with the line omitted, the build/rust-cfg don't have the has_virtual_leds line

build/rust-cfg

has_drtio
has_drtio_routing
has_grabber
has_si5324
has_siphaser
hw_rev="v1.1"
ki_impl="csr"
rtio_frequency="125.0"
si5324_soft_reset
Running `python src/gateware/kasli_soc.py -r build/pl.rs -c build/rustc-cfg -m build/mem.rs kasli-soc-satellite.json` with the line omitted, the `build/rust-cfg` don't have the `has_virtual_leds` line ### build/rust-cfg ``` has_drtio has_drtio_routing has_grabber has_si5324 has_siphaser hw_rev="v1.1" ki_impl="csr" rtio_frequency="125.0" si5324_soft_reset ```
sb10q commented 2023-08-29 11:58:17 +08:00
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https://github.com/m-labs/misoc/blob/master/misoc/integration/cpu_interface.py#L305

Please find out what is going on.

https://github.com/m-labs/misoc/blob/master/misoc/integration/cpu_interface.py#L305 Please find out what is going on.
sb10q commented 2023-08-29 12:00:41 +08:00
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You may want to check migen-axi as well - it might not share this code with misoc.

You may want to check migen-axi as well - it might not share this code with misoc.
morgan commented 2023-08-29 13:06:13 +08:00
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Difference between artiq and artiq-zynq

  • In artiq repo, the rust-cfg is generated by calling f.write(cpu_interface.get_rust_cfg(soc.get_csr_regions(), soc.get_constants())) in the misoc/integration/build.py.

    • get_rust_cfg analyze the content of soc.get_csr_regions() and soc.get_constants() to carefully obtain the useful string and output it to the rust-cfg file

  • While in artiq-zynq, the write_rustc_cfg_file(soc, filename) is called to generated rust-cfg in src/gateware/kasli_soc.py

    • It copies the content of soc.rustc_cfg = dict() directly to rust-cfg file

rust cfg difference if using get_rust_cfg

  • The write_rustc_cfg_file(soc, filename) was modified to follow get_rust_cfg
  • Then run python src/gateware/kasli_soc.py -c build/rustc-cfg kasli-soc-satellite.json

rustc-cfg before modification

has_drtio
has_drtio_routing
has_grabber
has_si5324
has_siphaser
has_virtual_leds
hw_rev="v1.1"
ki_impl="csr"
rtio_frequency="125.0"
si5324_soft_reset

rustc-cfg after modification

has_cri_con
has_drtioaux0
has_drtioaux1
has_drtioaux2
has_drtioaux3
has_drtiorep0
has_drtiorep1
has_drtiorep2
has_drtiosat
has_grabber0
has_gt_drtio
has_identifier
has_routing_table
has_rtio
has_rtio_analyzer
has_rtio_dma
has_rtio_moninj
has_siphaser
has_sys_crg
has_virtual_leds
rtio_log_channel="54"

Relevant code snippet

kasli_soc.py before modification

...
def write_rustc_cfg_file(soc, filename):
    with open(filename, "w") as f:
        for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
            if v is None:
                f.write("{}\n".format(k))
            else:
                f.write("{}=\"{}\"\n".format(k, v))
...

kasli_soc.py after modification

...
def write_rustc_cfg_file(soc, filename):
    with open(filename, "w") as f:
        for name, origin, busword, obj in soc.get_csr_regions():
            f.write("{}".format("has_"+name.lower()+"\n"))
        for name, value in soc.get_constants():
            if name.upper().startswith("CONFIG_"):
                if value is None:
                    f.write("{}".format(name.lower()[7:]+"\n"))
                else:
                    f.write("{}".format(name.lower()[7:]+"=\""+str(value)+"\"\n"))
...
## Difference between artiq and artiq-zynq - In artiq repo, the rust-cfg is generated by calling `f.write(cpu_interface.get_rust_cfg(soc.get_csr_regions(), soc.get_constants()))` in the `misoc/integration/build.py`. - `get_rust_cfg` analyze the content of `soc.get_csr_regions()` and `soc.get_constants()` to carefully obtain the useful string and output it to the rust-cfg file - While in artiq-zynq, the `write_rustc_cfg_file(soc, filename)` is called to generated rust-cfg in `src/gateware/kasli_soc.py` - It copies the content of `soc.rustc_cfg = dict()` directly to rust-cfg file ## rust cfg difference if using `get_rust_cfg` - The `write_rustc_cfg_file(soc, filename)` was modified to follow `get_rust_cfg` - Then run `python src/gateware/kasli_soc.py -c build/rustc-cfg kasli-soc-satellite.json` ### rustc-cfg before modification ``` has_drtio has_drtio_routing has_grabber has_si5324 has_siphaser has_virtual_leds hw_rev="v1.1" ki_impl="csr" rtio_frequency="125.0" si5324_soft_reset ``` ### rustc-cfg after modification ``` has_cri_con has_drtioaux0 has_drtioaux1 has_drtioaux2 has_drtioaux3 has_drtiorep0 has_drtiorep1 has_drtiorep2 has_drtiosat has_grabber0 has_gt_drtio has_identifier has_routing_table has_rtio has_rtio_analyzer has_rtio_dma has_rtio_moninj has_siphaser has_sys_crg has_virtual_leds rtio_log_channel="54" ``` ## Relevant code snippet ### kasli_soc.py before modification ``` ... def write_rustc_cfg_file(soc, filename): with open(filename, "w") as f: for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)): if v is None: f.write("{}\n".format(k)) else: f.write("{}=\"{}\"\n".format(k, v)) ... ``` ### kasli_soc.py after modification ``` ... def write_rustc_cfg_file(soc, filename): with open(filename, "w") as f: for name, origin, busword, obj in soc.get_csr_regions(): f.write("{}".format("has_"+name.lower()+"\n")) for name, value in soc.get_constants(): if name.upper().startswith("CONFIG_"): if value is None: f.write("{}".format(name.lower()[7:]+"\n")) else: f.write("{}".format(name.lower()[7:]+"=\""+str(value)+"\"\n")) ... ```
sb10q commented 2023-08-29 13:33:08 +08:00
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Yeah we should try to avoid divergence with misoc.

Yeah we should try to avoid divergence with misoc.
self.submodules.virtual_leds = virtual_leds.VirtualLeds() self.submodules.virtual_leds = virtual_leds.VirtualLeds()
self.csr_devices.append("virtual_leds") self.csr_devices.append("virtual_leds")

1
src/libboard_artiq/src/io_expander.rs
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@ -152,6 +152,7 @@ impl IoExpander {
} }
pub fn service(&mut self, i2c: &mut i2c::I2c) -> Result<(), &'static str> { pub fn service(&mut self, i2c: &mut i2c::I2c) -> Result<(), &'static str> {
#[cfg(has_virtual_leds)]
for (led, port, bit) in self.virtual_led_mapping.iter() { for (led, port, bit) in self.virtual_led_mapping.iter() {
let level = unsafe { csr::virtual_leds::status_read() >> led & 1 }; let level = unsafe { csr::virtual_leds::status_read() >> led & 1 };
self.set(*port, *bit, level != 0); self.set(*port, *bit, level != 0);