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kasli_soc: enable clock buffer IBUFDS_GTE2 after system clock domain reset #239

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den512 wants to merge 1 commits from den512/artiq-zynq:sys_clk_issue_1 into master
pull from: den512/artiq-zynq:sys_clk_issue_1
merge into: M-Labs:master
Conversation 1 Commits 1 Files Changed 2 +3
2 changed files with 3 additions and 0 deletions
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Showing only changes of commit 0d97eeb56a - Show all commits

2
src/runtime/src/rtio_clocking.rs
View File

@ -84,6 +84,7 @@ fn init_rtio(timer: &mut GlobalTimer) {
panic!("SYS CLK did not switch");
}
unsafe {
pl::csr::sys_crg::clock_switch_write(1); //re-enable clock input buffer after system clock domain reset
pl::csr::rtio_core::reset_phy_write(1);
}
info!("SYS PLL locked");
@ -103,6 +104,7 @@ fn init_drtio(timer: &mut GlobalTimer) {
panic!("SYS CLK did not switch");
}
unsafe {
pl::csr::drtio_transceiver::stable_clkin_write(1); //re-enable clock input buffer after system clock domain reset
pl::csr::rtio_core::reset_phy_write(1);
pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
}

1
src/satman/src/main.rs
View File

@ -642,6 +642,7 @@ pub extern "C" fn main_core0() -> i32 {
}
unsafe {
csr::drtio_transceiver::stable_clkin_write(1); //re-enable clock input buffer after system clock domain reset
csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
}