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kasli_soc: enable clock buffer IBUFDS_GTE2 after system clock domain reset #239

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den512 wants to merge 1 commits from den512/artiq-zynq:sys_clk_issue_1 into master
pull from: den512/artiq-zynq:sys_clk_issue_1
merge into: M-Labs:master
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den512 commented 2023-06-27 13:00:08 +08:00
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esavkin reviewed 2023-06-27 13:03:27 +08:00
src/runtime/src/rtio_clocking.rs Outdated
@ -84,6 +84,7 @@ fn init_rtio(timer: &mut GlobalTimer) {
panic!("SYS CLK did not switch");
}
unsafe {
pl::csr::sys_crg::clock_switch_write(1); //renable input clock buffer after reset of sys clock domain
esavkin commented 2023-06-27 13:03:27 +08:00
Owner

I think there is an issue with spelling/wording: "renable"

I think there is an issue with spelling/wording: "renable"
den512 marked this conversation as resolved
den512 force-pushed sys_clk_issue_1 from af0c151166 to 0d97eeb56a 2023-06-27 13:46:29 +08:00 Compare
den512 commented 2023-06-27 13:56:46 +08:00
Poster

System clock switching issue will fix only with artiq PR "kasli-soc: change initialization of GTX transceivers. #2122"

System clock switching issue will fix only with artiq PR "kasli-soc: change initialization of GTX transceivers. #2122"
sb10q closed this pull request 2023-07-24 22:58:56 +08:00

Pull request closed

Please reopen this pull request to perform a merge.
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Reference: M-Labs/artiq-zynq#239
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