Fix mismatched signatures for the wide interface #229
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Reference: M-Labs/artiq-zynq#229
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Delete Branch "jcoates/artiq-zynq:fix-wide-interface"
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See #76.
Lists are passed by-reference from python code, and so should be
&CSlice<_>
notCSlice<_>
. This change was made for the cache already inae0d724bf8
, but not for the wide interface.A quick grep for
extern.*CSlice
suggests these are the only remaining functions with a mismatched signature.Seems to make sense. Did you actually test this?
Yes - connected an oscciliscope to a fastino and can confirm it produces the right voltages both using DMA and writing events directly.
There are still some other issues with using the wide interface (we're seeing a lot of RTIO collision errors), but I'm not sure if that's a Kasli-SoC specific issue. I want to test on Kasli 2.0 before reporting anything.