M-Labs/artiq-zynq
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RTIO/SYS Clock merge #212

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sb10q merged 30 commits from mwojcik/artiq-zynq:rtiosys_clk_merge into master 2023-02-17 15:52:43 +08:00
Conversation 5 Commits 30 Files Changed 9 +5 -2
1 changed files with 5 additions and 2 deletions
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Showing only changes of commit e6b9d5ebcb - Show all commits

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src/runtime/src/main.rs
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@ -22,6 +22,7 @@ use void::Void;
use libconfig::Config;
use libcortex_a9::l2c::enable_l2_cache;
use libboard_artiq::{logger, identifier_read, init_gateware, pl};
use embedded_hal::blocking::delay::DelayUs;
const ASYNC_ERROR_COLLISION: u8 = 1 << 0;
const ASYNC_ERROR_BUSY: u8 = 1 << 1;
@ -108,6 +109,9 @@ pub fn main_core0() {
info!("NAR3/Zynq7000 starting...");
init_gateware();
timer.delay_us(500); // wait for FCLK to switch and MMCM to lock
ram::init_alloc_core0();
gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts();
@ -143,7 +147,6 @@ pub fn main_core0() {
};
rtio_clocking::init(&mut timer, &cfg);
init_gateware();
task::spawn(report_async_rtio_errors());