M-Labs/artiq-zynq
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RTIO/SYS Clock merge #212

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sb10q merged 30 commits from mwojcik/artiq-zynq:rtiosys_clk_merge into master 2023-02-17 15:52:43 +08:00
Conversation 5 Commits 30 Files Changed 9 +13 -10
1 changed files with 13 additions and 10 deletions
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src/gateware/zc706.py
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@ -42,16 +42,17 @@ class SMAClkinForward(Module):
class CLK200BootstrapClock(Module): class CLK200BootstrapClock(Module):
def __init__(self, platform): def __init__(self, platform, freq=125e6):
self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True) self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
self.cd_bootstrap.clk.attr.add("keep") self.cd_bootstrap.clk.attr.add("keep")
clk200 = platform.request("clk200") clk200 = platform.request("clk200")
clk200_se = Signal() clk200_se = Signal()
pll_fb = Signal() pll_fb = Signal()
pll_clk125 = Signal() pll_clkout = Signal()
assert freq in [125e6, 100e6]
divide = int(1e9/freq)
self.specials += [ self.specials += [
Instance("IBUFDS", Instance("IBUFDS",
i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se), i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se),
@ -64,10 +65,10 @@ class CLK200BootstrapClock(Module):
# VCO @ 1GHz # VCO @ 1GHz
p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
# 125MHz for bootstrap # 125MHz/100MHz for bootstrap
p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_clk125, p_CLKOUT1_DIVIDE=divide, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_clkout,
), ),
Instance("BUFG", i_I=pll_clk125, o_O=self.cd_bootstrap.clk) Instance("BUFG", i_I=pll_clkout, o_O=self.cd_bootstrap.clk)
] ]
@ -234,12 +235,13 @@ class _MasterBase(SoCCore):
txout_buf = Signal() txout_buf = Signal()
gtx0 = self.drtio_transceiver.gtxs[0] gtx0 = self.drtio_transceiver.gtxs[0]
self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
self.submodules.bootstrap = CLK200BootstrapClock(platform) self.submodules.bootstrap = CLK200BootstrapClock(platform, clk_freq)
self.submodules.sys_crg = zynq_clocking.SYSCRG( self.submodules.sys_crg = zynq_clocking.SYSCRG(
self.platform, self.platform,
self.ps7, self.ps7,
txout_buf, txout_buf,
clk_sw=gtx0.tx_init.done) clk_sw=gtx0.tx_init.done,
freq=clk_freq)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
self.csr_devices.append("sys_crg") self.csr_devices.append("sys_crg")
@ -373,12 +375,13 @@ class _SatelliteBase(SoCCore):
"BUFG", "BUFG",
i_I=gtx0.txoutclk, i_I=gtx0.txoutclk,
o_O=txout_buf) o_O=txout_buf)
self.submodules.bootstrap = CLK200BootstrapClock(platform) self.submodules.bootstrap = CLK200BootstrapClock(platform, clk_freq)
self.submodules.sys_crg = zynq_clocking.SYSCRG( self.submodules.sys_crg = zynq_clocking.SYSCRG(
self.platform, self.platform,
self.ps7, self.ps7,
txout_buf, txout_buf,
clk_sw=gtx0.tx_init.done) clk_sw=gtx0.tx_init.done,
freq=clk_freq)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk) self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
self.csr_devices.append("sys_crg") self.csr_devices.append("sys_crg")