M-Labs/artiq-zynq
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RTIO/SYS Clock merge #212

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sb10q merged 30 commits from mwojcik/artiq-zynq:rtiosys_clk_merge into master 2023-02-17 15:52:43 +08:00
Conversation 5 Commits 30 Files Changed 9 +4 -4
2 changed files with 4 additions and 4 deletions
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3
src/gateware/kasli_soc.py
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@ -14,6 +14,7 @@ from misoc.integration import cpu_interface
from artiq.coredevice import jsondesc from artiq.coredevice import jsondesc
from artiq.gateware import rtio, eem_7series from artiq.gateware import rtio, eem_7series
from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
from artiq.gateware.rtio.phy import ttl_simple from artiq.gateware.rtio.phy import ttl_simple
from artiq.gateware.drtio.transceiver import gtx_7series from artiq.gateware.drtio.transceiver import gtx_7series
from artiq.gateware.drtio.siphaser import SiPhaser7Series from artiq.gateware.drtio.siphaser import SiPhaser7Series
@ -90,13 +91,13 @@ class GenericStandalone(SoCCore):
p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se), i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
] ]
fix_serdes_timing_path(platform)
self.crg = self.ps7 # HACK for eem_7series to find the clock self.crg = self.ps7 # HACK for eem_7series to find the clock
self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se) self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se)
self.csr_devices.append("sys_crg") self.csr_devices.append("sys_crg")
# another hack since ps7 itself does not have cd_sys anymore # another hack since ps7 itself does not have cd_sys anymore
self.crg.cd_sys = self.sys_crg.cd_sys self.crg.cd_sys = self.sys_crg.cd_sys
self.platform.add_period_constraint(self.sys_crg.cd_sys.clk, 8.)
self.rtio_channels = [] self.rtio_channels = []
has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"]) has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])

5
src/gateware/zynq_clocking.py
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@ -69,10 +69,10 @@ class SYSCRG(Module, AutoCSR):
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.cd_sys.clk.attr.add("keep") self.cd_sys.clk.attr.add("keep")
self.cd_bootstrap.clk.attr.add("keep")
pll_locked = Signal() pll_locked = Signal()
pll_sys = Signal() pll_sys = Signal()
pll_sys.attr.add("keep")
pll_sys4x = Signal() pll_sys4x = Signal()
fb_clk = Signal() fb_clk = Signal()
fclk_buf = Signal() fclk_buf = Signal()
@ -108,5 +108,4 @@ class SYSCRG(Module, AutoCSR):
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~ps7.fclk.reset_n[0]), AsyncResetSynchronizer(self.cd_sys, ~pll_locked | ~ps7.fclk.reset_n[0]),
] ]
platform.add_period_constraint(self.cd_bootstrap.clk, 8.) platform.add_false_path_constraints(self.cd_bootstrap.clk, main_clk)
platform.add_false_path_constraints(self.cd_sys.clk, self.cd_bootstrap.clk, main_clk)