M-Labs/artiq-zynq
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RTIO/SYS Clock merge #212

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sb10q merged 30 commits from mwojcik/artiq-zynq:rtiosys_clk_merge into master 2023-02-17 15:52:43 +08:00
Conversation 5 Commits 30 Files Changed 9 +5 -4
2 changed files with 5 additions and 4 deletions
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Showing only changes of commit 831079f95f - Show all commits

4
src/runtime/src/main.rs
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@ -111,6 +111,8 @@ pub fn main_core0() {
ram::init_alloc_core0(); ram::init_alloc_core0();
gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts(); gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts();
info!("gateware ident: {}", identifier_read(&mut [0; 64]));
i2c::init(); i2c::init();
#[cfg(feature = "target_kasli_soc")] #[cfg(feature = "target_kasli_soc")]
@ -141,9 +143,7 @@ pub fn main_core0() {
}; };
rtio_clocking::init(&mut timer, &cfg); rtio_clocking::init(&mut timer, &cfg);
init_gateware(); init_gateware();
info!("gateware ident: {}", identifier_read(&mut [0; 64]));
task::spawn(report_async_rtio_errors()); task::spawn(report_async_rtio_errors());

5
src/runtime/src/rtio_clocking.rs
View File

@ -72,12 +72,13 @@ fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
unsafe { unsafe {
pl::csr::sys_crg::clock_switch_write(1); pl::csr::sys_crg::clock_switch_write(1);
} }
timer.delay_ms(2); timer.delay_ms(10);
// if it's not locked, it will hang at the CSR.
unsafe { unsafe {
pl::csr::rtio_core::reset_phy_write(1); pl::csr::rtio_core::reset_phy_write(1);
} }
// if it's not locked, it will hang at the CSR.
info!("SYS PLL locked"); info!("SYS PLL locked");
} }
#[cfg(has_drtio)] #[cfg(has_drtio)]