src/gateware/zc706.py

@@ -123,9 +123,6 @@ def prepare_zc706_platform(platform):
     platform.toolchain.bitstream_commands.extend([
         "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
     ])
-    platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
-    platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
-
 
 class ZC706(SoCCore):
     def __init__(self, acpki=False):

src/gateware/zynq_clocking.py

@@ -82,7 +82,6 @@ class SYSCRG(Module, AutoCSR):
         pll_sys = Signal()
         pll_sys4x = Signal()
         fb_clk = Signal()
-        fclk_buf = Signal()
 
         self.submodules.clk_sw_fsm = ClockSwitchFSM()
 
@@ -102,8 +101,7 @@ class SYSCRG(Module, AutoCSR):
                      i_CLKINSEL=self.clk_sw_fsm.o_clk_sw,
 
                      # VCO @ 1.5GHz when using 125MHz input
-                     # FCLK on startup is ~42MHz, VCO below minimum
-                     # do not use SYS before FCLK is configured from PS
+                     # 1.2GHz for 100MHz (zc706)
                      p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
                      i_CLKFBIN=fb_clk,
                      i_RST=self.clk_sw_fsm.o_reset,

src/libboard_artiq/src/lib.rs

@@ -44,26 +44,3 @@ pub fn identifier_read(buf: &mut [u8]) -> &str {
         str::from_utf8_unchecked(&buf[..len as usize])
     }
 }
-
-pub fn init_gateware() {
-    // Set up PS->PL clocks
-    slcr::RegisterBlock::unlocked(|slcr| {
-        // As we are touching the mux, the clock may glitch, so reset the PL.
-        slcr.fpga_rst_ctrl.write(
-            slcr::FpgaRstCtrl::zeroed()
-                .fpga0_out_rst(true)
-                .fpga1_out_rst(true)
-                .fpga2_out_rst(true)
-                .fpga3_out_rst(true)
-        );
-        slcr.fpga0_clk_ctrl.write(
-            slcr::Fpga0ClkCtrl::zeroed()
-                .src_sel(slcr::PllSource::IoPll)
-                .divisor0(8)
-                .divisor1(1)
-        );
-        slcr.fpga_rst_ctrl.write(
-            slcr::FpgaRstCtrl::zeroed()
-        );
-    });
-}

src/runtime/src/main.rs

@@ -21,7 +21,7 @@ use nb;
 use void::Void;
 use libconfig::Config;
 use libcortex_a9::l2c::enable_l2_cache;
-use libboard_artiq::{logger, identifier_read, init_gateware, pl};
+use libboard_artiq::{logger, identifier_read, pl};
 
 const ASYNC_ERROR_COLLISION: u8 = 1 << 0;
 const ASYNC_ERROR_BUSY: u8 = 1 << 1;
@@ -108,8 +108,6 @@ pub fn main_core0() {
 
     info!("NAR3/Zynq7000 starting...");
 
-    init_gateware();
-
     ram::init_alloc_core0();
     gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts();
 

src/satman/src/main.rs

@@ -22,7 +22,7 @@ use libboard_zynq::{i2c::I2c, timer::GlobalTimer, time::Milliseconds, print, pri
 use libsupport_zynq::ram;
 #[cfg(has_si5324)]
 use libboard_artiq::si5324;
-use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read, init_gateware};
+use libboard_artiq::{pl::csr, drtio_routing, drtioaux, logger, identifier_read};
 use libcortex_a9::{spin_lock_yield, interrupt_handler, regs::{MPIDR, SP}, notify_spin_lock, asm, l2c::enable_l2_cache};
 use libregister::{RegisterW, RegisterR};
 
@@ -439,9 +439,6 @@ pub extern fn main_core0() -> i32 {
     buffer_logger.set_uart_log_level(log::LevelFilter::Info);
     buffer_logger.register();
     log::set_max_level(log::LevelFilter::Info);
-    
-    init_gateware();
-    timer.delay_us(500); // wait for FCLK to reset and PLL to lock
 
     info!("ARTIQ satellite manager starting...");
     info!("gateware ident {}", identifier_read(&mut [0; 64]));