Support channel names in RTIO errors #209

Merged
sb10q merged 3 commits from esavkin/artiq-zynq:1697-rtiomap into master 2023-01-09 12:35:56 +08:00
Owner
Closes https://github.com/m-labs/artiq/issues/1697
esavkin requested review from sb10q 2022-12-13 12:59:48 +08:00
sb10q reviewed 2022-12-13 17:11:50 +08:00
@ -74,3 +75,2 @@
artiq_raise!("RTIOUnderflow",
"RTIO underflow at {0} mu, channel {1}, slack {2} mu",
timestamp, channel as i64, timestamp - get_counter());
format!("RTIO underflow at channel {}:{}, {{1}} mu, slack {{2}} mu", channel, resolve_channel_name(channel as u32)),
Owner

No. It's not "at channel".

No. It's not "at channel".
sb10q reviewed 2022-12-13 17:12:41 +08:00
@ -335,0 +354,4 @@
}
Ok(())
} ).or_else(|err| {
error!("read_device_map: error reading `device_map` from config: {}", err);
Owner

Why do you have the "read_device_map:" prefix here and not just above?

Why do you have the "read_device_map:" prefix here and not just above?
sb10q reviewed 2022-12-13 17:15:24 +08:00
@ -9,6 +9,7 @@
#![feature(naked_functions)]
#![feature(asm)]
#[macro_use]
Owner

Why?

Why?
Author
Owner

format macro wasn't available

format macro wasn't available
Owner

I guess that works, but it will make porting this firmware to RISC-V later (to merge it with the main ARTIQ runtime) more difficult, since it relies on cache coherency which is not available on MiSoC/RISC-V.

I guess that works, but it will make porting this firmware to RISC-V later (to merge it with the main ARTIQ runtime) more difficult, since it relies on cache coherency which is not available on MiSoC/RISC-V.
Author
Owner

since it relies on cache coherency

So all resolve_channel_name calls should be made on the core1 (like in RISC-V version now)?

> since it relies on cache coherency So all `resolve_channel_name` calls should be made on the core1 (like in RISC-V version now)?
Owner

I suppose you meant core0.

As long as we're on Zynq your proposed solution is more or less acceptable (though a bit ugly with the implicit synchronization), but we'll probably have to change it when merging firmwares.

I suppose you meant core0. As long as we're on Zynq your proposed solution is more or less acceptable (though a bit ugly with the implicit synchronization), but we'll probably have to change it when merging firmwares.
esavkin force-pushed 1697-rtiomap from 3bc8c067d3 to 7420a584eb 2022-12-20 17:47:35 +08:00 Compare
esavkin force-pushed 1697-rtiomap from 7420a584eb to b249e69b4c 2022-12-21 10:53:52 +08:00 Compare
Author
Owner

Changed that behavior so that it is more similar to RISC-V implementation.

Changed that behavior so that it is more similar to RISC-V implementation.
sb10q reviewed 2023-01-03 11:12:39 +08:00
@ -248,2 +248,3 @@
write_i32(stream, exception.id as i32).await?;
write_exception_string(stream, exception.message).await?;
if exception.message.len() == usize::MAX {
Owner

Obviously, all review comments from the ARTIQ PR are also applicable here.

Obviously, all review comments from the ARTIQ PR are also applicable here.
esavkin marked this conversation as resolved
sb10q reviewed 2023-01-03 11:12:45 +08:00
sb10q reviewed 2023-01-03 11:12:50 +08:00
@ -248,2 +248,3 @@
write_i32(stream, exception.id as i32).await?;
write_exception_string(stream, exception.message).await?;
if exception.message.len() == usize::MAX {
Owner

Obviously, all review comments from the ARTIQ PR are also applicable here.

Obviously, all review comments from the ARTIQ PR are also applicable here.
Owner

Obviously, all review comments from the ARTIQ PR are also applicable here.

Obviously, all review comments from the ARTIQ PR are also applicable here.
esavkin marked this conversation as resolved
sb10q reviewed 2023-01-03 11:12:52 +08:00
@ -248,2 +248,3 @@
write_i32(stream, exception.id as i32).await?;
write_exception_string(stream, exception.message).await?;
if exception.message.len() == usize::MAX {
Owner

Obviously, all review comments from the ARTIQ PR are also applicable here.

Obviously, all review comments from the ARTIQ PR are also applicable here.
esavkin marked this conversation as resolved
sb10q reviewed 2023-01-03 11:12:52 +08:00
@ -248,2 +248,3 @@
write_i32(stream, exception.id as i32).await?;
write_exception_string(stream, exception.message).await?;
if exception.message.len() == usize::MAX {
Owner

Obviously, all review comments from the ARTIQ PR are also applicable here.

Obviously, all review comments from the ARTIQ PR are also applicable here.
sb10q reviewed 2023-01-03 11:15:24 +08:00
@ -200,3 +200,2 @@
artiq_raise!("RTIOUnderflow",
"RTIO underflow at {0} mu, channel {1}",
timestamp as i64, channel as i64, 0);
"RTIO underflow at {{1}} mu, channel {rtio_channel_info:0}",
Owner

Why is it {{1}} here and {1} in artiq?

Why is it ``{{1}}`` here and ``{1}`` in ``artiq``?
Owner

This remains unanswered and unaddressed.

This remains unanswered and unaddressed.
Author
Owner

In this version format! macro is used. In artiq - it is not

In this version `format!` macro is used. In artiq - it is not
sb10q reviewed 2023-01-03 11:17:30 +08:00
@ -220,3 +227,3 @@
Ok(Packet::DestinationOkReply) => (),
Ok(Packet::DestinationSequenceErrorReply { channel }) =>{
error!("[DEST#{}] RTIO sequence error involving channel 0x{:04x}", destination, channel);
error!("[DEST#{}] RTIO sequence error involving channel 0x{:04x}:{}", destination, channel, resolve_channel_name(channel));
Owner

Message format is inconsistent with artiq.

Message format is inconsistent with ``artiq``.
esavkin force-pushed 1697-rtiomap from b249e69b4c to 439653b02a 2023-01-04 17:35:47 +08:00 Compare
sb10q merged commit 6b3fa98d70 into master 2023-01-09 12:35:56 +08:00
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Reference: M-Labs/artiq-zynq#209
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