M-Labs/artiq-zynq
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Soft panic for RTIO PLL reasons #199

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sb10q merged 16 commits from mwojcik/artiq-zynq:pll_error into master 2022-10-21 17:56:34 +08:00
Conversation 8 Commits 16 Files Changed 4 +5 -1
1 changed files with 5 additions and 1 deletions
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Showing only changes of commit 4034be5da8 - Show all commits

6
src/runtime/src/kernel/core1.rs
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@ -5,11 +5,13 @@ use alloc::borrow::ToOwned;
use log::{debug, info, error};
use cslice::CSlice;
use libregister::RegisterR;
use libcortex_a9::{
enable_fpu,
cache::{dcci_slice, iciallu, bpiall},
asm::{dsb, isb},
sync_channel,
regs::MPIDR
};
use libboard_zynq::{mpcore, gic};
use libsupport_zynq::ram;
@ -219,7 +221,9 @@ extern fn dl_unwind_find_exidx(pc: *const u32, len_ptr: *mut u32) -> *const u32
let length;
let start: *const EXIDX_Entry;
unsafe {
if &__text_start as *const u32 <= pc && pc < &__text_end as *const u32 {
let id = MPIDR.read().cpu_id() as usize;
// try to look up kernel for core 1 only
if (&__text_start as *const u32 <= pc && pc < &__text_end as *const u32) || id == 0 {
length = (&__exidx_end as *const EXIDX_Entry).offset_from(&__exidx_start) as u32;
start = &__exidx_start;
} else {