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Soft panic for RTIO PLL reasons #199

Merged
sb10q merged 16 commits from mwojcik/artiq-zynq:pll_error into master 2022-10-21 17:56:34 +08:00
Conversation 8 Commits 16 Files Changed 4 +10 -25
2 changed files with 10 additions and 25 deletions
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Showing only changes of commit 052cae9df7 - Show all commits

2
src/runtime/src/main.rs
View File

@ -122,7 +122,7 @@ pub fn main_core0() {
}; };
task::spawn(report_async_rtio_errors()); task::spawn(report_async_rtio_errors());
rtio_clocking::init(&mut timer, &cfg).expect("Could not set up RTIO PLL"); rtio_clocking::init(&mut timer, &cfg);
comms::main(timer, cfg); comms::main(timer, cfg);

33
src/runtime/src/rtio_clocking.rs
View File

@ -1,4 +1,4 @@
use log::{info, warn, error}; use log::{info, warn};
use libboard_zynq::timer::GlobalTimer; use libboard_zynq::timer::GlobalTimer;
use embedded_hal::blocking::delay::DelayMs; use embedded_hal::blocking::delay::DelayMs;
use libconfig::Config; use libconfig::Config;
@ -9,7 +9,6 @@ use libboard_zynq::i2c::I2c;
use crate::i2c; use crate::i2c;
#[cfg(has_si5324)] #[cfg(has_si5324)]
use libboard_artiq::si5324; use libboard_artiq::si5324;
#[derive(Debug, PartialEq, Copy, Clone)] #[derive(Debug, PartialEq, Copy, Clone)]
#[allow(non_camel_case_types)] #[allow(non_camel_case_types)]
pub enum RtioClock { pub enum RtioClock {
@ -22,7 +21,6 @@ pub enum RtioClock {
Ext0_Synth0_100to125, Ext0_Synth0_100to125,
Ext0_Synth0_125to125, Ext0_Synth0_125to125,
} }
#[allow(unreachable_code)] #[allow(unreachable_code)]
fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock { fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
let mut res = RtioClock::Default; let mut res = RtioClock::Default;
@ -65,9 +63,7 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
} }
res res
} }
fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) {
fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) -> Result<(), &'static str> {
#[cfg(has_rtio_crg_clock_sel)] #[cfg(has_rtio_crg_clock_sel)]
let clock_sel = match _clk { let clock_sel = match _clk {
RtioClock::Ext0_Bypass => { RtioClock::Ext0_Bypass => {
@ -83,7 +79,6 @@ fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) -> Result<(), &'static st
0 0
} }
}; };
unsafe { unsafe {
pl::csr::rtio_crg::pll_reset_write(1); pl::csr::rtio_crg::pll_reset_write(1);
#[cfg(has_rtio_crg_clock_sel)] #[cfg(has_rtio_crg_clock_sel)]
@ -95,17 +90,12 @@ fn init_rtio(timer: &mut GlobalTimer, _clk: RtioClock) -> Result<(), &'static st
if locked { if locked {
info!("RTIO PLL locked"); info!("RTIO PLL locked");
} else { } else {
error!("RTIO PLL failed to lock"); panic!("RTIO PLL failed to lock");
return Err("RTIO PLL failed to lock");
} }
unsafe { unsafe {
pl::csr::rtio_core::reset_phy_write(1); pl::csr::rtio_core::reset_phy_write(1);
} }
Ok(())
} }
#[cfg(has_drtio)] #[cfg(has_drtio)]
fn init_drtio(timer: &mut GlobalTimer) fn init_drtio(timer: &mut GlobalTimer)
{ {
@ -117,9 +107,8 @@ fn init_drtio(timer: &mut GlobalTimer)
pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
} }
} }
#[cfg(has_si5324)] #[cfg(has_si5324)]
fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) -> Result<(), &'static str> { fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) {
let (si5324_settings, si5324_ref_input) = match clk { let (si5324_settings, si5324_ref_input) = match clk {
RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
info!("using 10MHz reference to make 125MHz RTIO clock with PLL"); info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
@ -234,24 +223,20 @@ fn setup_si5324(i2c: &mut I2c, timer: &mut GlobalTimer, clk: RtioClock) -> Resul
) )
} }
}; };
si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer) si5324::setup(i2c, &si5324_settings, si5324_ref_input, timer).expect("cannot initialize Si5324");
} }
pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
pub fn init(timer: &mut GlobalTimer, cfg: &Config) -> Result<(), &'static str> {
let clk = get_rtio_clock_cfg(cfg); let clk = get_rtio_clock_cfg(cfg);
#[cfg(has_si5324)] #[cfg(has_si5324)]
{ {
let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() }; let i2c = unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() };
let si5324_ext_input = si5324::Input::Ckin1; let si5324_ext_input = si5324::Input::Ckin1;
match clk { match clk {
RtioClock::Ext0_Bypass => si5324::bypass(i2c, si5324_ext_input, timer), RtioClock::Ext0_Bypass => si5324::bypass(i2c, si5324_ext_input, timer).expect("cannot bypass Si5324"),
_ => setup_si5324(i2c, timer, clk), _ => setup_si5324(i2c, timer, clk),
}?; }
} }
#[cfg(has_drtio)] #[cfg(has_drtio)]
init_drtio(timer); init_drtio(timer);
init_rtio(timer, clk)?; init_rtio(timer, clk);
Ok(())
} }