libdwarf: make catch type field singly referenced #192

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sb10q merged 1 commits from occheung/artiq-zynq:target2-rel into master 2022-05-31 18:26:30 +08:00
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Description

This PR changes the parsing of the exception type of an exception entry in the .ARM.extab section, from doubly referenced to singly referenced.

ARTIQ PR 1898

Background

Compiler generates a R_ARM_TARGET2 relocation that points to the exception type for the linker. By default, ld.lld resolves R_ARM_TARGET2 using "got-prel", which

  • inserts an entry into the GOT that references the exception type; and
  • relocate the relative offset of the GOT entry to PC.
    It results in exception type being doubly referenced. By specifying the option --target2=rel to ld.lld, the R_ARM_TARGET2 relocation is instead resolved as a relative address offset to the exception type. It bypasses the generation of a GOT entry.

This PR consist of the changes such that the exception type field is read as a singly referenced value. The change of ld.lld options is in the corresponding patch to mainline ARTIQ.

## Description This PR changes the parsing of the exception type of an exception entry in the `.ARM.extab` section, from doubly referenced to singly referenced. ### Related PR [ARTIQ PR 1898](https://github.com/m-labs/artiq/pull/1898) ### Background Compiler generates a `R_ARM_TARGET2` relocation that points to the exception type for the linker. By default, ld.lld resolves `R_ARM_TARGET2` using "got-prel", which - inserts an entry into the GOT that references the exception type; and - relocate the relative offset of the GOT entry to PC. It results in exception type being doubly referenced. By specifying the option `--target2=rel` to ld.lld, the `R_ARM_TARGET2` relocation is instead resolved as a relative address offset to the exception type. It bypasses the generation of a GOT entry. This PR consist of the changes such that the exception type field is read as a singly referenced value. The change of ld.lld options is in the corresponding patch to mainline ARTIQ.
occheung added 1 commit 2022-05-30 18:03:31 +08:00
sb10q merged commit f0febe0ee4 into master 2022-05-31 18:26:30 +08:00
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Reference: M-Labs/artiq-zynq#192
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