From 5f247bb09e078f7f9e7123baa5fed02e031993aa Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 26 Nov 2021 13:29:06 +0800 Subject: [PATCH 1/4] add switch for drtio 100mhz clock --- src/gateware/zc706.py | 45 ++++++++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index aceb2e9..d78d2eb 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -127,7 +127,7 @@ def prepare_zc706_platform(platform): class ZC706(SoCCore): - def __init__(self, acpki=False): + def __init__(self, acpki=False, _drtio100mhz=False): self.acpki = acpki self.rustc_cfg = dict() @@ -181,7 +181,7 @@ class ZC706(SoCCore): class _MasterBase(SoCCore): - def __init__(self, acpki=False): + def __init__(self, acpki=False, drtio100mhz=False): self.acpki = acpki self.rustc_cfg = dict() @@ -195,6 +195,7 @@ class _MasterBase(SoCCore): platform.add_extension(si5324_fmc33) self.sys_clk_freq = 125e6 + rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq platform = self.platform @@ -208,7 +209,8 @@ class _MasterBase(SoCCore): self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), pads=data_pads, - sys_clk_freq=self.sys_clk_freq) + sys_clk_freq=self.sys_clk_freq, + rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) @@ -313,7 +315,7 @@ class _MasterBase(SoCCore): class _SatelliteBase(SoCCore): - def __init__(self, acpki=False): + def __init__(self, acpki=False, drtio100mhz=False): self.acpki = acpki self.rustc_cfg = dict() @@ -327,6 +329,7 @@ class _SatelliteBase(SoCCore): platform.add_extension(si5324_fmc33) self.sys_clk_freq = 125e6 + rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq platform = self.platform # SFP @@ -342,7 +345,8 @@ class _SatelliteBase(SoCCore): self.submodules.drtio_transceiver = gtx_7series.GTX( clock_pads=platform.request("si5324_clkout"), pads=data_pads, - sys_clk_freq=self.sys_clk_freq) + sys_clk_freq=self.sys_clk_freq, + rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") drtioaux_csr_group = [] @@ -399,7 +403,7 @@ class _SatelliteBase(SoCCore): self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, - ultrascale=False, + ultrascale=True, rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) platform.add_false_path_constraints( self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output) @@ -595,34 +599,33 @@ class _NIST_QC2_RTIO: class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO): - def __init__(self, acpki): - ZC706.__init__(self, acpki) + def __init__(self, acpki, drtio100mhz): + ZC706.__init__(self, acpki, drtio100mhz) _NIST_CLOCK_RTIO.__init__(self) class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO): - def __init__(self, acpki): - _MasterBase.__init__(self, acpki) - + def __init__(self, acpki, drtio100mhz): + _MasterBase.__init__(self, acpki, drtio100mhz) _NIST_CLOCK_RTIO.__init__(self) class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO): - def __init__(self, acpki): - _SatelliteBase.__init__(self, acpki) + def __init__(self, acpki, drtio100mhz): + _SatelliteBase.__init__(self, acpki, drtio100mhz) _NIST_CLOCK_RTIO.__init__(self) class NIST_QC2(ZC706, _NIST_QC2_RTIO): - def __init__(self, acpki): - ZC706.__init__(self, acpki) + def __init__(self, acpki, drtio100mhz): + ZC706.__init__(self, acpki, drtio100mhz) _NIST_QC2_RTIO.__init__(self) class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO): - def __init__(self, acpki): - _MasterBase.__init__(self, acpki) + def __init__(self, acpki, drtio100mhz): + _MasterBase.__init__(self, acpki, drtio100mhz) _NIST_QC2_RTIO.__init__(self) class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO): - def __init__(self, acpki): - _SatelliteBase.__init__(self, acpki) + def __init__(self, acpki, drtio100mhz): + _SatelliteBase.__init__(self, acpki, drtio100mhz) _NIST_QC2_RTIO.__init__(self) @@ -661,6 +664,8 @@ def main(): help="build Rust compiler configuration into the specified file") parser.add_argument("-g", default=None, help="build gateware into the specified directory") + parser.add_argument("--drtio100mhz", action="store_true", default=False, + help="DRTIO variants only: use 100MHz DRTIO clock") parser.add_argument("-V", "--variant", default="nist_clock", help="variant: " "[acpki_]nist_clock/nist_qc2[_master/_satellite] " @@ -676,7 +681,7 @@ def main(): except KeyError: raise SystemExit("Invalid variant (-V/--variant)") - soc = cls(acpki=acpki) + soc = cls(acpki=acpki, drtio100mhz=args.drtio100mhz) soc.finalize() if args.r is not None: -- 2.47.0 From 015ec8e88f7c6c2779a1382192e9f674091cad78 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Mon, 29 Nov 2021 13:03:21 +0800 Subject: [PATCH 2/4] restore ultrascale --- src/gateware/zc706.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index d78d2eb..58c0f30 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -403,7 +403,7 @@ class _SatelliteBase(SoCCore): self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer, - ultrascale=True, + ultrascale=False, rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq) platform.add_false_path_constraints( self.ps7.cd_sys.clk, self.siphaser.mmcm_freerun_output) -- 2.47.0 From f1b1a8303a2528e4453a2cb95432529cb47959a1 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 1 Dec 2021 16:25:00 +0800 Subject: [PATCH 3/4] drtio: * add 100mhz variants, * si5324 settings for sat * rtio_clocking: additional default 100mhz option --- default.nix | 9 ++++++++- src/gateware/zc706.py | 18 +++++++++--------- src/runtime/src/rtio_clocking.rs | 18 ++++++++++++++++-- src/satman/src/main.rs | 15 ++++++++++++++- 4 files changed, 47 insertions(+), 13 deletions(-) diff --git a/default.nix b/default.nix index d2dc606..777f786 100644 --- a/default.nix +++ b/default.nix @@ -8,7 +8,10 @@ let vivado = import { inherit pkgs; }; # FSBL configuration supplied by Vivado 2020.1 for these boards: fsblTargets = ["zc702" "zc706" "zed"]; - sat_variants = ["satellite" "nist_clock_satellite" "nist_qc2_satellite" "acpki_nist_clock_satellite" "acpki_nist_qc2_satellite"]; + sat_variants = [ + "nist_clock_satellite" "nist_qc2_satellite" "acpki_nist_clock_satellite" "acpki_nist_qc2_satellite" + "nist_clock_satellite_100mhz" "nist_qc2_satellite_100mhz" "acpki_nist_clock_satellite_100mhz" "acpki_nist_qc2_satellite_100mhz" + ]; build = { target, variant, json ? null }: let szl = (import zynq-rs)."${target}-szl"; fsbl = import "${zynq-rs}/nix/fsbl.nix" { @@ -136,15 +139,19 @@ in (build { target = "zc706"; variant = "nist_clock"; }) // (build { target = "zc706"; variant = "nist_clock_master"; }) // (build { target = "zc706"; variant = "nist_clock_satellite"; }) // + (build { target = "zc706"; variant = "nist_clock_satellite_100mhz"; }) // (build { target = "zc706"; variant = "nist_qc2"; }) // (build { target = "zc706"; variant = "nist_qc2_master"; }) // (build { target = "zc706"; variant = "nist_qc2_satellite"; }) // + (build { target = "zc706"; variant = "nist_qc2_satellite_100mhz"; }) // (build { target = "zc706"; variant = "acpki_nist_clock"; }) // (build { target = "zc706"; variant = "acpki_nist_clock_master"; }) // (build { target = "zc706"; variant = "acpki_nist_clock_satellite"; }) // + (build { target = "zc706"; variant = "acpki_nist_clock_satellite_100mhz"; }) // (build { target = "zc706"; variant = "acpki_nist_qc2"; }) // (build { target = "zc706"; variant = "acpki_nist_qc2_master"; }) // (build { target = "zc706"; variant = "acpki_nist_qc2_satellite"; }) // + (build { target = "zc706"; variant = "acpki_nist_qc2_satellite_100mhz"; }) // (build { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) // (build { target = "kasli_soc"; variant = "master"; json = ./kasli-soc-master.json; }) // (build { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; }) // diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 58c0f30..de61bb4 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -127,7 +127,7 @@ def prepare_zc706_platform(platform): class ZC706(SoCCore): - def __init__(self, acpki=False, _drtio100mhz=False): + def __init__(self, acpki=False): self.acpki = acpki self.rustc_cfg = dict() @@ -249,7 +249,7 @@ class _MasterBase(SoCCore): self.add_csr_group("drtioaux", drtioaux_csr_group) self.add_memory_group("drtioaux_mem", drtioaux_memory_group) - self.rustc_cfg["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) + self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6) self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n) self.csr_devices.append("si5324_rst_n") @@ -600,7 +600,7 @@ class _NIST_QC2_RTIO: class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO): def __init__(self, acpki, drtio100mhz): - ZC706.__init__(self, acpki, drtio100mhz) + ZC706.__init__(self, acpki) _NIST_CLOCK_RTIO.__init__(self) class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO): @@ -615,7 +615,7 @@ class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO): class NIST_QC2(ZC706, _NIST_QC2_RTIO): def __init__(self, acpki, drtio100mhz): - ZC706.__init__(self, acpki, drtio100mhz) + ZC706.__init__(self, acpki) _NIST_QC2_RTIO.__init__(self) class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO): @@ -628,7 +628,6 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO): _SatelliteBase.__init__(self, acpki, drtio100mhz) _NIST_QC2_RTIO.__init__(self) - VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite, NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]} @@ -664,11 +663,9 @@ def main(): help="build Rust compiler configuration into the specified file") parser.add_argument("-g", default=None, help="build gateware into the specified directory") - parser.add_argument("--drtio100mhz", action="store_true", default=False, - help="DRTIO variants only: use 100MHz DRTIO clock") parser.add_argument("-V", "--variant", default="nist_clock", help="variant: " - "[acpki_]nist_clock/nist_qc2[_master/_satellite] " + "[acpki_]nist_clock/nist_qc2[_master/_satellite][_100mhz]" "(default: %(default)s)") args = parser.parse_args() @@ -676,12 +673,15 @@ def main(): acpki = variant.startswith("acpki_") if acpki: variant = variant[6:] + drtio100mhz = variant.endswith("_100mhz") + if drtio100mhz: + variant = variant[:-7] try: cls = VARIANTS[variant] except KeyError: raise SystemExit("Invalid variant (-V/--variant)") - soc = cls(acpki=acpki, drtio100mhz=args.drtio100mhz) + soc = cls(acpki=acpki, drtio100mhz=drtio100mhz) soc.finalize() if args.r is not None: diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs index a3e2f7b..36f3405 100644 --- a/src/runtime/src/rtio_clocking.rs +++ b/src/runtime/src/rtio_clocking.rs @@ -23,6 +23,7 @@ pub enum RtioClock { Ext0_Synth0_125to125, } +#[allow(unreachable_code)] fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock { let mut res = RtioClock::Default; if let Ok(clk) = cfg.read_str("rtio_clock") { @@ -46,8 +47,21 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock { warn!("error reading configuration. Falling back to default."); } if res == RtioClock::Default { - warn!("Using default configuration - internal 125MHz RTIO clock."); - return RtioClock::Int_125; + #[cfg(rtio_frequency="100.0")] + { + warn!("Using default configuration - internal 100MHz RTIO clock."); + return RtioClock::Int_100; + } + #[cfg(rtio_frequency="125.0")] + { + warn!("Using default configuration - internal 125MHz RTIO clock."); + return RtioClock::Int_125; + } + // anything else + { + warn!("Using default configuration - internal 125MHz RTIO clock."); + return RtioClock::Int_125; + } } res } diff --git a/src/satman/src/main.rs b/src/satman/src/main.rs index 5c05e25..69693a1 100644 --- a/src/satman/src/main.rs +++ b/src/satman/src/main.rs @@ -398,7 +398,7 @@ fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) { } } -#[cfg(has_si5324)] +#[cfg(all(has_si5324, rtio_frequency = "125.0"))] const SI5324_SETTINGS: si5324::FrequencySettings = si5324::FrequencySettings { n1_hs : 5, @@ -411,6 +411,19 @@ const SI5324_SETTINGS: si5324::FrequencySettings crystal_ref: true }; +#[cfg(all(has_si5324, rtio_frequency = "100.0"))] +const SI5324_SETTINGS: si5324::FrequencySettings + = si5324::FrequencySettings { + n1_hs : 5, + nc1_ls : 10, + n2_hs : 10, + n2_ls : 250, + n31 : 50, + n32 : 50, + bwsel : 4, + crystal_ref: true +}; + static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17]; #[no_mangle] -- 2.47.0 From fff5e8fe1eafba50f623f7cdf891713b734e705c Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 3 Dec 2021 11:18:25 +0800 Subject: [PATCH 4/4] kasli_soc: custom (incl 100mhz) rtio_freq support --- src/gateware/kasli_soc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gateware/kasli_soc.py b/src/gateware/kasli_soc.py index da376ea..c4defe2 100755 --- a/src/gateware/kasli_soc.py +++ b/src/gateware/kasli_soc.py @@ -180,7 +180,7 @@ class GenericStandalone(SoCCore): class GenericMaster(SoCCore): def __init__(self, description, acpki=False): sys_clk_freq = 125e6 - rtio_clk_freq = 125e6 + rtio_clk_freq = description["rtio_frequency"] self.acpki = acpki self.rustc_cfg = dict() @@ -300,7 +300,7 @@ class GenericMaster(SoCCore): class GenericSatellite(SoCCore): def __init__(self, description, acpki=False): sys_clk_freq = 125e6 - rtio_clk_freq = 125e6 + rtio_clk_freq = description["rtio_frequency"] self.acpki = acpki self.rustc_cfg = dict() -- 2.47.0