M-Labs/artiq-zynq
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Clock input settings improvements #152

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sb10q merged 12 commits from mwojcik/artiq-zynq:clock_input_improv into master 2021-11-29 11:18:00 +08:00
Conversation 7 Commits 12 Files Changed 4 +10 -5
1 changed files with 10 additions and 5 deletions
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Showing only changes of commit ee3b1715cb - Show all commits

15
src/runtime/src/rtio_clocking.rs
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@ -24,8 +24,9 @@ pub enum RtioClock {
}
fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
let mut res = RtioClock::Default;
if let Ok(clk) = cfg.read_str("rtio_clock") {
match clk.as_ref() {
res = match clk.as_ref() {
"int_125" => RtioClock::Int_125,
"int_100" => RtioClock::Int_100,
"int_150" => RtioClock::Int_150,
@ -37,14 +38,18 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
"ext0_synth0_125to125" => RtioClock::Ext0_Synth0_125to125,
_ => {
warn!("Unrecognised rtio_clock setting. Falling back to default.");
RtioClock::Int_125
RtioClock::Default
}
}
};
}
else {
info!("error reading configuration. Falling back to default.");
RtioClock::Default
warn!("error reading configuration. Falling back to default.");
}
if res == RtioClock::Default {
warn!("Using default configuration - internal 125MHz RTIO clock.");
return RtioClock::Int_125;
}
res
}