M-Labs/artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests 1 Releases Wiki Activity

Clock input settings improvements #152

Merged
sb10q merged 12 commits from mwojcik/artiq-zynq:clock_input_improv into master 2021-11-29 11:18:00 +08:00
Conversation 7 Commits 12 Files Changed 4 +10 -3
1 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files
Showing only changes of commit c94582ccbe - Show all commits

13
src/runtime/src/rtio_clocking.rs
View File

@ -35,6 +35,7 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
} }
} }
else { else {
info!("error reading configuration. Using default internal 125MHz clock");
RtioClock::Int_125 RtioClock::Int_125
} }
} }
@ -105,16 +106,22 @@ fn setup_si5324(timer: &mut GlobalTimer, clk: RtioClock) {
crystal_ref: true crystal_ref: true
}); });
} }
let si5324_ref_input = si5324::Input::Ckin2;
si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() }, si5324::setup(unsafe { (&mut i2c::I2C_BUS).as_mut().unwrap() },
&si5324_settings.unwrap(), si5324::Input::Ckin2, timer).expect("cannot initialize Si5324"); &si5324_settings.unwrap(), si5324_ref_input, timer).expect("cannot initialize Si5324");
} }
pub fn init(timer: &mut GlobalTimer, cfg: &Config) { pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
let clk = get_rtio_clock_cfg(cfg); let clk = get_rtio_clock_cfg(cfg);
#[cfg(has_si5324)] #[cfg(has_si5324)]
setup_si5324(timer, clk); {
let si5324_ext_input = si5324::Input::Ckin2;
match clk {
RtioClock::Ext0_Bypass => si5324::bypass(si5324_ext_input).expect("cannot bypass Si5324"),
_ => setup_si5324(timer, clk),
}
}
#[cfg(has_drtio)] #[cfg(has_drtio)]
init_drtio(timer); init_drtio(timer);