M-Labs/artiq-zynq
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zc706: added dummy spi #149

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mwojcik merged 2 commits from mwojcik/artiq-zynq:zc706_dummy_spi into master 2021-10-14 16:38:06 +08:00
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1 changed files with 4 additions and 4 deletions
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src/gateware/zc706.py
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@ -106,8 +106,8 @@ _ams101_dac = [
) )
] ]
_dummy_spi = [ _pmod_spi = [
("dummy_spi", 0, ("pmod_spi", 0,
# PMOD_1 4-7 pins, same bank as sfp_tx_disable or user_sma_clock # PMOD_1 4-7 pins, same bank as sfp_tx_disable or user_sma_clock
Subsignal("miso", Pins("Y20"), IOStandard("LVCMOS25")), Subsignal("miso", Pins("Y20"), IOStandard("LVCMOS25")),
Subsignal("clk", Pins("AA20"), IOStandard("LVCMOS25")), Subsignal("clk", Pins("AA20"), IOStandard("LVCMOS25")),
@ -467,7 +467,7 @@ class _NIST_CLOCK_RTIO:
platform.add_extension(leds_fmc33) platform.add_extension(leds_fmc33)
platform.add_extension(pmod1_33) platform.add_extension(pmod1_33)
platform.add_extension(_ams101_dac) platform.add_extension(_ams101_dac)
platform.add_extension(_dummy_spi) platform.add_extension(_pmod_spi)
rtio_channels = [] rtio_channels = []
@ -516,7 +516,7 @@ class _NIST_CLOCK_RTIO:
phy, ififo_depth=128)) phy, ififo_depth=128))
# no SDIO on PL side, dummy SPI placeholder instead # no SDIO on PL side, dummy SPI placeholder instead
phy = spi2.SPIMaster(platform.request("dummy_spi")) phy = spi2.SPIMaster(platform.request("pmod_spi"))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))