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boot fails on NIST board #94

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opened 2020-08-25 10:27:43 +08:00 by sb10q · 5 comments
sb10q commented 2020-08-25 10:27:43 +08:00
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Tried with:

  • Build 86469 of job artiq:zc706-nist_qc2-sd
  • Build 86461 of job artiq:zc706-nist_clock-sd
  • Build 86484 of job artiq:zc706-simple-sd
                     __________   __
                    / ___/__  /  / /
                    \__ \  / /  / /
                   ___/ / / /__/ /___
                  /____/ /____/_____/

                   (C) 2020 M-Labs

[     0.020091s]  INFO(szl): Simple Zynq Loader starting...
[     0.025305s] DEBUG(szl): FPU enabled on Core0
[     0.029653s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 1600000000 Hz
[     0.010010s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz
[     0.017227s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1333333332 Hz
[     0.024686s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 666666660/444444440
[     0.031837s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 9876543 Hz (divisors=3*45)
[     0.042235s]  INFO(szl): decompressing payload
LZMA error: LZMA data is corrupt
[     0.050811s] ERROR(szl): decompression failed
Tried with: * Build 86469 of job artiq:zc706-nist_qc2-sd * Build 86461 of job artiq:zc706-nist_clock-sd * Build 86484 of job artiq:zc706-simple-sd ```text __________ __ / ___/__ / / / \__ \ / / / / ___/ / / /__/ /___ /____/ /____/_____/ (C) 2020 M-Labs [ 0.020091s] INFO(szl): Simple Zynq Loader starting... [ 0.025305s] DEBUG(szl): FPU enabled on Core0 [ 0.029653s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 1600000000 Hz [ 0.010010s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz [ 0.017227s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1333333332 Hz [ 0.024686s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 666666660/444444440 [ 0.031837s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 9876543 Hz (divisors=3*45) [ 0.042235s] INFO(szl): decompressing payload LZMA error: LZMA data is corrupt [ 0.050811s] ERROR(szl): decompression failed ```
pca006132 commented 2020-08-25 10:33:17 +08:00
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This problem also occur before when the L2 cache is not configured correctly, but it is gone after configuring the cache and the maintenance operations properly.

However, I think the current master do not have L2 cache enabled yet?

This problem also occur before when the L2 cache is not configured correctly, but it is gone after configuring the cache and the maintenance operations properly. However, I think the current master do not have L2 cache enabled yet?
sb10q commented 2020-08-25 10:37:34 +08:00
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Probably another bug in the DDR system which shows up on the slightly different hardware they have. The current master passes HITL CI which involves the SDRAM...

Probably another bug in the DDR system which shows up on the slightly different hardware they have. The current master passes HITL CI which involves the SDRAM...
sb10q commented 2020-08-25 10:38:44 +08:00
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I will re-enable the FSBL images and ask them to test. Eventually we'll probably need access to a problematic board...

I will re-enable the FSBL images and ask them to test. Eventually we'll probably need access to a problematic board...
sb10q commented 2020-08-26 10:54:32 +08:00
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Their board works with FSBL.

Xilinx First Stage Boot Loader
Release 2019.2  Jan  1 1970-00:00:01
Devcfg driver initialized
Silicon Version 3.1
Boot mode is SD
SD: rc= 0
SD Init Done
Flash Base Address: 0xE0100000
Reboot status register: 0x60400000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 3
Partition Number: 1
Header Dump
Image Word Len: 0x00089AC5
Data Word Len: 0x00089AC5
Partition Word Len:0x00089AC5
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000075D0
Partition Attr: 0x00000020
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFE5B76F
Bitstream
In FsblHookBeforeBitstreamDload function
PCAP:StatusReg = 0x40000A30
PCAP:device ready
PCAP:Clear done
Level Shifter Value = 0xA
Devcfg Status register = 0x40000A30
PCAP:Fabric is Initialized done
PCAP register dump:
PCAP CTRL 0xF8007000: 0x4C00E07F
PCAP LOCK 0xF8007004: 0x0000001A
PCAP CONFIG 0xF8007008: 0x00000508
PCAP ISR 0xF800700C: 0x0802000B
PCAP IMR 0xF8007010: 0xFFFFFFFF
PCAP STATUS 0xF8007014: 0x00000A30
PCAP DMA SRC ADDR 0xF8007018: 0x00100001
PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF
PCAP DMA SRC LEN 0xF8007020: 0x00089AC5
PCAP DMA DEST LEN 0xF8007024: 0x00089AC5
PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF
PCAP MBOOT 0xF800702C: 0x0000C000
PCAP SW ID 0xF8007030: 0x00000000
PCAP UNLOCK 0xF8007034: 0x757BDF0D
PCAP MCTRL 0xF8007080: 0x30800100

DMA Done !

FPGA Done !
In FsblHookAfterBitstreamDload function
Partition Number: 2
Header Dump
Image Word Len: 0x0001842E
Data Word Len: 0x0001842E
Partition Word Len:0x0001842E
Load Addr: 0x00100000
Exec Addr: 0x0010016C
Partition Start: 0x000910A0
Partition Attr: 0x00000010
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFD25EF8
Application
Handoff Address: 0x0010016C
In FsblHookBeforeHandoff function
SUCCESSFUL_HANDOFF
FSBL Status = 0x1
[     0.002362s]  INFO(runtime): NAR3/Zynq7000 starting...
[     0.007698s]  INFO(runtime): gateware already loaded
[     0.012671s]  INFO(runtime): detected gateware: acpki_Simple
[     0.020005s] DEBUG(libboard_zynq::sdio): Reset SDIO!
[     0.024975s] DEBUG(libboard_zynq::sdio): Changing clock frequency to 400000
[     0.059169s] DEBUG(libboard_zynq::sdio): Changing clock frequency to 25000000
[     0.066331s] DEBUG(libboard_zynq::sdio::sd_card): Getting bus width
[     0.075522s] DEBUG(libboard_zynq::sdio::sd_card): 4 bit support
[     0.081446s] DEBUG(libboard_zynq::sdio::sd_card): Changing bus width
[     0.089005s] DEBUG(libboard_zynq::sdio): Set block size to 512
[     0.099589s] DEBUG(runtime::sd_reader): Partition ID: C
[     0.109293s]  INFO(runtime): using internal RTIO clock (default)
[     0.117005s]  INFO(runtime): RTIO PLL locked
[     0.126952s]  INFO(runtime::comms): network addresses: MAC=00-0a-35-04-f6-50 IPv4=10.0.0.240 IPv6-LL=fe80::20a:35ff:fe04:f650 IPv6=no configured address
[     0.140760s] DEBUG(libboard_zynq::eth): Eth TX clock for 125000000: 999999990 / 1 / 8 = 124999998
[     0.150710s] DEBUG(runtime::kernel::core1): Core1 started
[     0.156121s] DEBUG(runtime::kernel::core1): FPU enabled on Core1
[     0.166946s] DEBUG(runtime::analyzer): arming RTIO analyzer
[     3.183775s]  INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Full }
[     3.191649s] DEBUG(libboard_zynq::eth): Eth TX clock for 125000000: 999999990 / 1 / 8 = 124999998
Their board works with FSBL. ```text Xilinx First Stage Boot Loader Release 2019.2 Jan 1 1970-00:00:01 Devcfg driver initialized Silicon Version 3.1 Boot mode is SD SD: rc= 0 SD Init Done Flash Base Address: 0xE0100000 Reboot status register: 0x60400000 Multiboot Register: 0x0000C000 Image Start Address: 0x00000000 Partition Header Offset:0x00000C80 Partition Count: 3 Partition Number: 1 Header Dump Image Word Len: 0x00089AC5 Data Word Len: 0x00089AC5 Partition Word Len:0x00089AC5 Load Addr: 0x00000000 Exec Addr: 0x00000000 Partition Start: 0x000075D0 Partition Attr: 0x00000020 Partition Checksum Offset: 0x00000000 Section Count: 0x00000001 Checksum: 0xFFE5B76F Bitstream In FsblHookBeforeBitstreamDload function PCAP:StatusReg = 0x40000A30 PCAP:device ready PCAP:Clear done Level Shifter Value = 0xA Devcfg Status register = 0x40000A30 PCAP:Fabric is Initialized done PCAP register dump: PCAP CTRL 0xF8007000: 0x4C00E07F PCAP LOCK 0xF8007004: 0x0000001A PCAP CONFIG 0xF8007008: 0x00000508 PCAP ISR 0xF800700C: 0x0802000B PCAP IMR 0xF8007010: 0xFFFFFFFF PCAP STATUS 0xF8007014: 0x00000A30 PCAP DMA SRC ADDR 0xF8007018: 0x00100001 PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF PCAP DMA SRC LEN 0xF8007020: 0x00089AC5 PCAP DMA DEST LEN 0xF8007024: 0x00089AC5 PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF PCAP MBOOT 0xF800702C: 0x0000C000 PCAP SW ID 0xF8007030: 0x00000000 PCAP UNLOCK 0xF8007034: 0x757BDF0D PCAP MCTRL 0xF8007080: 0x30800100 DMA Done ! FPGA Done ! In FsblHookAfterBitstreamDload function Partition Number: 2 Header Dump Image Word Len: 0x0001842E Data Word Len: 0x0001842E Partition Word Len:0x0001842E Load Addr: 0x00100000 Exec Addr: 0x0010016C Partition Start: 0x000910A0 Partition Attr: 0x00000010 Partition Checksum Offset: 0x00000000 Section Count: 0x00000001 Checksum: 0xFFD25EF8 Application Handoff Address: 0x0010016C In FsblHookBeforeHandoff function SUCCESSFUL_HANDOFF FSBL Status = 0x1 [ 0.002362s] INFO(runtime): NAR3/Zynq7000 starting... [ 0.007698s] INFO(runtime): gateware already loaded [ 0.012671s] INFO(runtime): detected gateware: acpki_Simple [ 0.020005s] DEBUG(libboard_zynq::sdio): Reset SDIO! [ 0.024975s] DEBUG(libboard_zynq::sdio): Changing clock frequency to 400000 [ 0.059169s] DEBUG(libboard_zynq::sdio): Changing clock frequency to 25000000 [ 0.066331s] DEBUG(libboard_zynq::sdio::sd_card): Getting bus width [ 0.075522s] DEBUG(libboard_zynq::sdio::sd_card): 4 bit support [ 0.081446s] DEBUG(libboard_zynq::sdio::sd_card): Changing bus width [ 0.089005s] DEBUG(libboard_zynq::sdio): Set block size to 512 [ 0.099589s] DEBUG(runtime::sd_reader): Partition ID: C [ 0.109293s] INFO(runtime): using internal RTIO clock (default) [ 0.117005s] INFO(runtime): RTIO PLL locked [ 0.126952s] INFO(runtime::comms): network addresses: MAC=00-0a-35-04-f6-50 IPv4=10.0.0.240 IPv6-LL=fe80::20a:35ff:fe04:f650 IPv6=no configured address [ 0.140760s] DEBUG(libboard_zynq::eth): Eth TX clock for 125000000: 999999990 / 1 / 8 = 124999998 [ 0.150710s] DEBUG(runtime::kernel::core1): Core1 started [ 0.156121s] DEBUG(runtime::kernel::core1): FPU enabled on Core1 [ 0.166946s] DEBUG(runtime::analyzer): arming RTIO analyzer [ 3.183775s] INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Full } [ 3.191649s] DEBUG(libboard_zynq::eth): Eth TX clock for 125000000: 999999990 / 1 / 8 = 124999998 ```
sb10q commented 2021-02-02 09:37:49 +08:00
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Seems resolved.

Seems resolved.
sb10q closed this issue 2021-02-02 09:37:49 +08:00
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Reference: M-Labs/artiq-zynq#94
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