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implement core device cache #62

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opened 2020-07-16 19:02:44 +08:00 by sb10q · 1 comment
sb10q commented 2020-07-16 19:02:44 +08:00
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Probably makes sense to look into this only after the two-cpu alloc architecture is sorted out.

Probably makes sense to look into this only after the two-cpu alloc architecture is sorted out.
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 label 2020-07-16 19:02:44 +08:00
sb10q commented 2020-07-25 17:06:23 +08:00
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Done, will need managing the Cache object with core0 and do message-passing if we end up doing core1 resets.

Done, will need managing the Cache object with core0 and do message-passing if we end up doing core1 resets.
sb10q closed this issue 2020-07-25 17:06:25 +08:00
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Reference: M-Labs/artiq-zynq#62
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