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BootROM process from SD card breaks DDR #5

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opened 2020-05-01 15:29:23 +08:00 by sb10q · 18 comments
sb10q commented 2020-05-01 15:29:23 +08:00
Owner

Copy the boot.bin from the zc706-sd derivation to a SD card, set the switches to SD card boot, reset/powercycle the ZC706, and this happens:

[     0.000002s]  INFO(szl): Simple Zynq Loader starting
[     0.005456s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 1600000000 Hz
[     0.003454s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz[     0.010598s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1333333332 Hz
[     0.017989s]  INFO(libboard_zynq::ddr): DDR 3x/2x clocks: 666666660/444444440
[     0.025089s]  INFO(libboard_zynq::ddr): DDR DCI clock: 10582010 Hz
[     0.031909s]  INFO(szl): decompressing payload
[     0.036388s] ERROR(szl): LZMA error: LZMA data is corrupt
[     0.041692s] ERROR(szl): decompression failed

Same szl ELF binary works fine via JTAG.

Copy the ``boot.bin`` from the ``zc706-sd`` derivation to a SD card, set the switches to SD card boot, reset/powercycle the ZC706, and this happens: ```text [ 0.000002s] INFO(szl): Simple Zynq Loader starting [ 0.005456s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 1600000000 Hz [ 0.003454s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz[ 0.010598s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1333333332 Hz [ 0.017989s] INFO(libboard_zynq::ddr): DDR 3x/2x clocks: 666666660/444444440 [ 0.025089s] INFO(libboard_zynq::ddr): DDR DCI clock: 10582010 Hz [ 0.031909s] INFO(szl): decompressing payload [ 0.036388s] ERROR(szl): LZMA error: LZMA data is corrupt [ 0.041692s] ERROR(szl): decompression failed ``` Same szl ELF binary works fine via JTAG.
sb10q commented 2020-05-01 15:55:27 +08:00
Poster
Owner

boot.bin files created using the official Vivado bootgen are also affected by this bug.

``boot.bin`` files created using the official Vivado bootgen are also affected by this bug.
astro commented 2020-05-04 06:26:38 +08:00

I've seen random memory corruption like this before when not doing xilinx_ps7_init in openocd before running with JTAG. I guess we are missing some initialization...

I've seen random memory corruption like this before when not doing `xilinx_ps7_init` in openocd before running with JTAG. I guess we are missing some initialization...
astro commented 2020-05-04 07:28:33 +08:00

I have a hunch that ddr.memtest() will fail in this scenario. Could you please run one?

I'm back to comparing register values with a few ps7_init.* files.

I have a hunch that `ddr.memtest()` will fail in this scenario. Could you please run one? I'm back to comparing register values with a few ps7_init.* files.
sb10q commented 2020-05-04 17:37:10 +08:00
Poster
Owner

Indeed, it breaks when booting from SD:

[     0.000002s]  INFO(szl): Simple Zynq Loader starting
[     0.005530s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 1600000000 Hz
[     0.003477s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz
[     0.010690s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1333333332 Hz
[     0.018151s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 666666660/444444440
[     0.025268s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10582010 Hz
[     0.031936s]  INFO(libboard_zynq::ddr): memtest phase 0 (status: Normal)
511 MB Ok
[     3.757024s]  INFO(libboard_zynq::ddr): memtest phase 1 (status: Normal)
[     3.763708s] ERROR(libboard_zynq::ddr): 00100000: expected FFFFFFFF, read FF00FF00
[     3.771260s] ERROR(libboard_zynq::ddr): 00100008: expected FFFFFFFF, read FFFFFF55
[     3.778812s] ERROR(libboard_zynq::ddr): 00100024: expected FFFFFFFF, read 555555FF
[     3.786363s] ERROR(libboard_zynq::ddr): 00100028: expected FFFFFFFF, read 55555555
[     3.793915s] ERROR(libboard_zynq::ddr): 00100044: expected FFFFFFFF, read 55F555FF
[     3.801466s] ERROR(libboard_zynq::ddr): 00100048: expected FFFFFFFF, read 55555555
[     3.809019s] ERROR(libboard_zynq::ddr): 00100064: expected FFFFFFFF, read 55F555FF
[     3.816569s] ERROR(libboard_zynq::ddr): 00100068: expected FFFFFFFF, read 55555555
[     3.824122s] ERROR(libboard_zynq::ddr): 00100084: expected FFFFFFFF, read 5755D5FF
[     3.831672s] ERROR(libboard_zynq::ddr): 00100088: expected FFFFFFFF, read 55555555
[     3.839225s] ERROR(libboard_zynq::ddr): 001000A4: expected FFFFFFFF, read FF75FF55
[     3.846776s] ERROR(libboard_zynq::ddr): 001000A8: expected FFFFFFFF, read 55555555
[     3.854328s] ERROR(libboard_zynq::ddr): 001000C4: expected FFFFFFFF, read 5755D5FF
[     3.861879s] ERROR(libboard_zynq::ddr): 001000C8: expected FFFFFFFF, read 55555555
[     3.869431s] ERROR(libboard_zynq::ddr): 001000E4: expected FFFFFFFF, read 57FFD555
[errors continue...]

And works when booting from JTAG:

[     0.000000s]  INFO(szl): Simple Zynq Loader starting
[     0.005131s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 1600000000 Hz
[     0.010355s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz
[     0.017579s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1333333332 Hz
[     0.025039s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 666666660/444444440
[     0.032157s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10582010 Hz
[     0.041119s]  INFO(libboard_zynq::ddr): memtest phase 0 (status: Normal)
511 MB Ok
[     3.766178s]  INFO(libboard_zynq::ddr): memtest phase 1 (status: Normal)
511 MB Ok
[    25.089293s]  INFO(libboard_zynq::ddr): memtest phase 2 (status: Normal)
511 MB Ok
[    46.412407s]  INFO(libboard_zynq::ddr): memtest phase 3 (status: Normal)
511 MB Ok
[    67.735522s]  INFO(szl): decompressing payload
[    67.783422s]  INFO(szl): executing payload
[     0.000003s]  INFO(runtime): NAR3 starting...
[     0.004612s]  INFO(runtime): Detected gateware: RTIO_ZC706
[     0.012937s] DEBUG(runtime::kernel): Core1 started
[     3.537915s]  INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Half }

I think all the init code should be moved to szl, the OpenOCD side should just ensure the bare minimum, i.e. that the core runs and that the OCM is correctly configured.

Indeed, it breaks when booting from SD: ```text [ 0.000002s] INFO(szl): Simple Zynq Loader starting [ 0.005530s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 1600000000 Hz [ 0.003477s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz [ 0.010690s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1333333332 Hz [ 0.018151s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 666666660/444444440 [ 0.025268s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10582010 Hz [ 0.031936s] INFO(libboard_zynq::ddr): memtest phase 0 (status: Normal) 511 MB Ok [ 3.757024s] INFO(libboard_zynq::ddr): memtest phase 1 (status: Normal) [ 3.763708s] ERROR(libboard_zynq::ddr): 00100000: expected FFFFFFFF, read FF00FF00 [ 3.771260s] ERROR(libboard_zynq::ddr): 00100008: expected FFFFFFFF, read FFFFFF55 [ 3.778812s] ERROR(libboard_zynq::ddr): 00100024: expected FFFFFFFF, read 555555FF [ 3.786363s] ERROR(libboard_zynq::ddr): 00100028: expected FFFFFFFF, read 55555555 [ 3.793915s] ERROR(libboard_zynq::ddr): 00100044: expected FFFFFFFF, read 55F555FF [ 3.801466s] ERROR(libboard_zynq::ddr): 00100048: expected FFFFFFFF, read 55555555 [ 3.809019s] ERROR(libboard_zynq::ddr): 00100064: expected FFFFFFFF, read 55F555FF [ 3.816569s] ERROR(libboard_zynq::ddr): 00100068: expected FFFFFFFF, read 55555555 [ 3.824122s] ERROR(libboard_zynq::ddr): 00100084: expected FFFFFFFF, read 5755D5FF [ 3.831672s] ERROR(libboard_zynq::ddr): 00100088: expected FFFFFFFF, read 55555555 [ 3.839225s] ERROR(libboard_zynq::ddr): 001000A4: expected FFFFFFFF, read FF75FF55 [ 3.846776s] ERROR(libboard_zynq::ddr): 001000A8: expected FFFFFFFF, read 55555555 [ 3.854328s] ERROR(libboard_zynq::ddr): 001000C4: expected FFFFFFFF, read 5755D5FF [ 3.861879s] ERROR(libboard_zynq::ddr): 001000C8: expected FFFFFFFF, read 55555555 [ 3.869431s] ERROR(libboard_zynq::ddr): 001000E4: expected FFFFFFFF, read 57FFD555 [errors continue...] ``` And works when booting from JTAG: ```text [ 0.000000s] INFO(szl): Simple Zynq Loader starting [ 0.005131s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 1600000000 Hz [ 0.010355s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz [ 0.017579s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1333333332 Hz [ 0.025039s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 666666660/444444440 [ 0.032157s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10582010 Hz [ 0.041119s] INFO(libboard_zynq::ddr): memtest phase 0 (status: Normal) 511 MB Ok [ 3.766178s] INFO(libboard_zynq::ddr): memtest phase 1 (status: Normal) 511 MB Ok [ 25.089293s] INFO(libboard_zynq::ddr): memtest phase 2 (status: Normal) 511 MB Ok [ 46.412407s] INFO(libboard_zynq::ddr): memtest phase 3 (status: Normal) 511 MB Ok [ 67.735522s] INFO(szl): decompressing payload [ 67.783422s] INFO(szl): executing payload [ 0.000003s] INFO(runtime): NAR3 starting... [ 0.004612s] INFO(runtime): Detected gateware: RTIO_ZC706 [ 0.012937s] DEBUG(runtime::kernel): Core1 started [ 3.537915s] INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Half } ``` I think all the init code should be moved to ``szl``, the OpenOCD side should just ensure the bare minimum, i.e. that the core runs and that the OCM is correctly configured.
sb10q commented 2020-05-06 17:42:12 +08:00
Poster
Owner

NB: this can be worked around by using the FSBL:

Xilinx First Stage Boot Loader 

Release 2019.2  Mar 10 2020-11:47:47

Devcfg driver initialized 

Silicon Version 3.1

Boot mode is SD

SD: rc= 0

SD Init Done 

Flash Base Address: 0xE0100000

Reboot status register: 0x60400000

Multiboot Register: 0x0000C000

Image Start Address: 0x00000000

Partition Header Offset:0x00000C80

Partition Count: 3

Partition Number: 1

Header Dump

Image Word Len: 0x00065D23

Data Word Len: 0x00065D23

Partition Word Len:0x00065D23

Load Addr: 0x00000000

Exec Addr: 0x00000000

Partition Start: 0x000075D0

Partition Attr: 0x00000020

Partition Checksum Offset: 0x00000000

Section Count: 0x00000001

Checksum: 0xFFEC7055

Bitstream

In FsblHookBeforeBitstreamDload function 

PCAP:StatusReg = 0x40000A30

PCAP:device ready

PCAP:Clear done

Level Shifter Value = 0xA 

Devcfg Status register = 0x40000A30 

PCAP:Fabric is Initialized done

PCAP register dump:

PCAP CTRL 0xF8007000: 0x4C00E07F

PCAP LOCK 0xF8007004: 0x0000001A

PCAP CONFIG 0xF8007008: 0x00000508

PCAP ISR 0xF800700C: 0x0802000B

PCAP IMR 0xF8007010: 0xFFFFFFFF

PCAP STATUS 0xF8007014: 0x50000F30

PCAP DMA SRC ADDR 0xF8007018: 0x00100001

PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF

PCAP DMA SRC LEN 0xF8007020: 0x00065D23

PCAP DMA DEST LEN 0xF8007024: 0x00065D23

PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF

PCAP MBOOT 0xF800702C: 0x0000C000

PCAP SW ID 0xF8007030: 0x00000000

PCAP UNLOCK 0xF8007034: 0x757BDF0D

PCAP MCTRL 0xF8007080: 0x30800100



DMA Done ! 



FPGA Done ! 

In FsblHookAfterBitstreamDload function 

Partition Number: 2

Header Dump

Image Word Len: 0x00008C83

Data Word Len: 0x00008C83

Partition Word Len:0x00008C83

Load Addr: 0x00100000

Exec Addr: 0x00100020

Partition Start: 0x0006D300

Partition Attr: 0x00000010

Partition Checksum Offset: 0x00000000

Section Count: 0x00000001

Checksum: 0xFFD784E5

Application

Handoff Address: 0x00100020

In FsblHookBeforeHandoff function 

SUCCESSFUL_HANDOFF

FSBL Status = 0x1

[     0.000003s]  INFO(runtime): NAR3 starting...
[     0.004670s]  INFO(runtime): gateware already loaded
[     0.009631s]  INFO(runtime): detected gateware: RTIO_ZC706
[     2.968390s]  INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Half }

Core1 is not working with the FSBL however, and also FSBL is ugly.

NB: this can be worked around by using the FSBL: ```text Xilinx First Stage Boot Loader Release 2019.2 Mar 10 2020-11:47:47 Devcfg driver initialized Silicon Version 3.1 Boot mode is SD SD: rc= 0 SD Init Done Flash Base Address: 0xE0100000 Reboot status register: 0x60400000 Multiboot Register: 0x0000C000 Image Start Address: 0x00000000 Partition Header Offset:0x00000C80 Partition Count: 3 Partition Number: 1 Header Dump Image Word Len: 0x00065D23 Data Word Len: 0x00065D23 Partition Word Len:0x00065D23 Load Addr: 0x00000000 Exec Addr: 0x00000000 Partition Start: 0x000075D0 Partition Attr: 0x00000020 Partition Checksum Offset: 0x00000000 Section Count: 0x00000001 Checksum: 0xFFEC7055 Bitstream In FsblHookBeforeBitstreamDload function PCAP:StatusReg = 0x40000A30 PCAP:device ready PCAP:Clear done Level Shifter Value = 0xA Devcfg Status register = 0x40000A30 PCAP:Fabric is Initialized done PCAP register dump: PCAP CTRL 0xF8007000: 0x4C00E07F PCAP LOCK 0xF8007004: 0x0000001A PCAP CONFIG 0xF8007008: 0x00000508 PCAP ISR 0xF800700C: 0x0802000B PCAP IMR 0xF8007010: 0xFFFFFFFF PCAP STATUS 0xF8007014: 0x50000F30 PCAP DMA SRC ADDR 0xF8007018: 0x00100001 PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF PCAP DMA SRC LEN 0xF8007020: 0x00065D23 PCAP DMA DEST LEN 0xF8007024: 0x00065D23 PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF PCAP MBOOT 0xF800702C: 0x0000C000 PCAP SW ID 0xF8007030: 0x00000000 PCAP UNLOCK 0xF8007034: 0x757BDF0D PCAP MCTRL 0xF8007080: 0x30800100 DMA Done ! FPGA Done ! In FsblHookAfterBitstreamDload function Partition Number: 2 Header Dump Image Word Len: 0x00008C83 Data Word Len: 0x00008C83 Partition Word Len:0x00008C83 Load Addr: 0x00100000 Exec Addr: 0x00100020 Partition Start: 0x0006D300 Partition Attr: 0x00000010 Partition Checksum Offset: 0x00000000 Section Count: 0x00000001 Checksum: 0xFFD784E5 Application Handoff Address: 0x00100020 In FsblHookBeforeHandoff function SUCCESSFUL_HANDOFF FSBL Status = 0x1 [ 0.000003s] INFO(runtime): NAR3 starting... [ 0.004670s] INFO(runtime): gateware already loaded [ 0.009631s] INFO(runtime): detected gateware: RTIO_ZC706 [ 2.968390s] INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Half } ``` Core1 is not working with the FSBL however, and also FSBL is ugly.
sb10q commented 2020-05-06 22:23:51 +08:00
Poster
Owner

Core1 from FSBL should work now, will test tomorrow.

Update: It works!

Core1 from FSBL should work now, will test tomorrow. Update: It works!
sb10q changed title from BootROM process from SD card corrupts LZMA data to BootROM process from SD card breaks DDR 2020-05-07 14:51:18 +08:00
astro was assigned by sb10q 2020-05-07 14:51:44 +08:00
sb10q commented 2020-05-11 11:20:44 +08:00
Poster
Owner

The issue still occurs after 0c48dd934e

The issue still occurs after https://git.m-labs.hk/M-Labs/zc706/commit/0c48dd934eb65e1cbd0124200ae2e08c7049c903
sb10q commented 2020-06-25 20:22:49 +08:00
Poster
Owner

This makes SDRAM work with SZL, on both boards:

diff --git a/src/szl/src/main.rs b/src/szl/src/main.rs
index 8b89469..616a062 100644
--- a/src/szl/src/main.rs
+++ b/src/szl/src/main.rs
@@ -12,6 +12,7 @@ use libboard_zynq::{
     self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
     logger,
     timer::GlobalTimer,
+    ps7_init,
 };
 use libsupport_zynq as _;
 
@@ -33,13 +34,17 @@ pub fn main_core0() {
     log::set_max_level(log::LevelFilter::Debug);
     info!("Simple Zynq Loader starting...");
 
+    ps7_init::apply();
+    libboard_zynq::stdio::drop_uart();
+
     const CPU_FREQ: u32 = 800_000_000;
 
     ArmPll::setup(2 * CPU_FREQ);
     Clocks::set_cpu_freq(CPU_FREQ);
     IoPll::setup(1_000_000_000);
-    libboard_zynq::stdio::drop_uart(); // reinitialize UART after clocking change
+    zynq::stdio::drop_uart(); // reinitialize UART after clocking change
     let mut ddr = zynq::ddr::DdrRam::new();
+    ddr.memtest();
 
     let payload = include_bytes!("../../../build/szl-payload.bin.lzma");
     info!("decompressing payload");

I guess we can now bisect the list of registers in ps7_init, and find out which one(s) are necessary to make the SDRAM work.

This makes SDRAM work with SZL, on both boards: ``` diff --git a/src/szl/src/main.rs b/src/szl/src/main.rs index 8b89469..616a062 100644 --- a/src/szl/src/main.rs +++ b/src/szl/src/main.rs @@ -12,6 +12,7 @@ use libboard_zynq::{ self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll}, logger, timer::GlobalTimer, + ps7_init, }; use libsupport_zynq as _; @@ -33,13 +34,17 @@ pub fn main_core0() { log::set_max_level(log::LevelFilter::Debug); info!("Simple Zynq Loader starting..."); + ps7_init::apply(); + libboard_zynq::stdio::drop_uart(); + const CPU_FREQ: u32 = 800_000_000; ArmPll::setup(2 * CPU_FREQ); Clocks::set_cpu_freq(CPU_FREQ); IoPll::setup(1_000_000_000); - libboard_zynq::stdio::drop_uart(); // reinitialize UART after clocking change + zynq::stdio::drop_uart(); // reinitialize UART after clocking change let mut ddr = zynq::ddr::DdrRam::new(); + ddr.memtest(); let payload = include_bytes!("../../../build/szl-payload.bin.lzma"); info!("decompressing payload"); ``` I guess we can now bisect the list of registers in ps7_init, and find out which one(s) are necessary to make the SDRAM work.
pca006132 commented 2020-06-25 22:28:55 +08:00

I guess we can now bisect the list of registers in ps7_init, and find out which one(s) are necessary to make the SDRAM work.

Run report_differences and check the results?

> I guess we can now bisect the list of registers in ps7_init, and find out which one(s) are necessary to make the SDRAM work. Run `report_differences` and check the results?
sb10q commented 2020-06-26 10:08:35 +08:00
Poster
Owner

AFAIK Astro already did that without success, so bisecting the register writes while checking if the memtest still passes seems like the way to go.

AFAIK Astro already did that without success, so bisecting the register writes while checking if the memtest still passes seems like the way to go.
pca006132 commented 2020-07-02 17:34:40 +08:00 
pub const INIT_DATA: &'static [InitOp] = &[
    MaskWrite(0xF8006014, 0x1FFFFF, 0x4159B),
    MaskWrite(0xF800601C, 0xFFFFFFFF, 0x720238E5),
    MaskWrite(0xF8006030, 0xFFFFFFFF, 0x40930),
    MaskWrite(0xF8006050, 0xFF0F8FFF, 0x77010800),
    MaskWrite(0xF80060B0, 0x1FFFFFFF, 0x1CFFFFFF),
    MaskWrite(0xF80060B8, 0x1FFFFFF, 0x200066),
    MaskWrite(0xF8006138, 0xFFFFF, 0x3B821),
    MaskWrite(0xF8006194, 0xFFFFF, 0x1FC82),
];

This is the minimal set of init data required to boot properly, i.e. successfully decompressing the lzma buffer. Removing anyone would cause the RAM to fail. Not sure if this is sufficient to ensure no memory corruption, as I've only boot the board and have not yet tried to run kernel on it.

@astro

```rust pub const INIT_DATA: &'static [InitOp] = &[ MaskWrite(0xF8006014, 0x1FFFFF, 0x4159B), MaskWrite(0xF800601C, 0xFFFFFFFF, 0x720238E5), MaskWrite(0xF8006030, 0xFFFFFFFF, 0x40930), MaskWrite(0xF8006050, 0xFF0F8FFF, 0x77010800), MaskWrite(0xF80060B0, 0x1FFFFFFF, 0x1CFFFFFF), MaskWrite(0xF80060B8, 0x1FFFFFF, 0x200066), MaskWrite(0xF8006138, 0xFFFFF, 0x3B821), MaskWrite(0xF8006194, 0xFFFFF, 0x1FC82), ]; ``` This is the minimal set of init data required to boot properly, i.e. successfully decompressing the lzma buffer. Removing anyone would cause the RAM to fail. Not sure if this is sufficient to ensure no memory corruption, as I've only boot the board and have not yet tried to run kernel on it. @astro
sb10q commented 2020-07-02 22:07:00 +08:00
Poster
Owner

Note comments in ps7_init. Those are DDRC registers, e.g.

    // .. .. reg_ddrc_t_rc = 0x1b
    // .. .. ==> 0xF8006014[5:0] = 0x0000001BU
    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
    // .. .. reg_ddrc_t_rfc_min = 0x56
    // .. .. ==> 0xF8006014[13:6] = 0x00000056U
    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
    // .. .. ==> 0xF8006014[20:14] = 0x00000010U
    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
    // .. ..
Note comments in ps7_init. Those are DDRC registers, e.g. ```text // .. .. reg_ddrc_t_rc = 0x1b // .. .. ==> 0xF8006014[5:0] = 0x0000001BU // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU // .. .. reg_ddrc_t_rfc_min = 0x56 // .. .. ==> 0xF8006014[13:6] = 0x00000056U // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 // .. .. ==> 0xF8006014[20:14] = 0x00000010U // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U // .. .. ```
astro commented 2020-07-03 08:21:56 +08:00

Awesome, thank you!

f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f adds these to our DDR initialization.

Awesome, thank you! f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f adds these to our DDR initialization.
pca006132 commented 2020-07-03 10:00:44 +08:00

f0697c3ec3 does not work.

diff --git a/src/Cargo.lock b/src/Cargo.lock
index 138023f..90701c2 100644
--- a/src/Cargo.lock
+++ b/src/Cargo.lock
@@ -200,7 +200,7 @@ dependencies = [
 [[package]]
 name = "libasync"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f"
 dependencies = [
  "embedded-hal",
  "libcortex_a9",
@@ -212,7 +212,7 @@ dependencies = [
 [[package]]
 name = "libboard_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f"
 dependencies = [
  "bit_field",
  "embedded-hal",
@@ -236,7 +236,7 @@ dependencies = [
 [[package]]
 name = "libcortex_a9"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f"
 dependencies = [
  "bit_field",
  "libregister",
@@ -245,7 +245,7 @@ dependencies = [
 [[package]]
 name = "libregister"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f"
 dependencies = [
  "bit_field",
  "vcell",
@@ -255,7 +255,7 @@ dependencies = [
 [[package]]
 name = "libsupport_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908"
+source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f"
 dependencies = [
  "compiler_builtins",
  "libboard_zynq",
diff --git a/src/szl/src/main.rs b/src/szl/src/main.rs
index 56d0ea8..46e7c8d 100644
--- a/src/szl/src/main.rs
+++ b/src/szl/src/main.rs
@@ -12,7 +12,6 @@ use libcortex_a9::cache::dcci_slice;
 use libboard_zynq::{
     self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
     logger,
-    ps7_init,
     timer::GlobalTimer,
 };
 use libsupport_zynq as _;
@@ -30,12 +29,11 @@ extern fn lzma_error(message: *const u8) {
 
 #[no_mangle]
 pub fn main_core0() {
-    ps7_init::apply();
-
     GlobalTimer::start();
     logger::init().unwrap();
     log::set_max_level(log::LevelFilter::Debug);
     info!("Simple Zynq Loader starting...");
+    info!("NO PS7 INIT!");
 
     unsafe {
         llvm_asm!("

Still memory corrupted:

[     0.000002s]  INFO(szl): Simple Zynq Loader starting...
[     0.005790s]  INFO(szl): NO PS7 INIT!
[     0.009443s]  INFO(szl): FPU enabled on Core0
[     0.013792s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 1600000000 Hz
[     0.005714s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz
[     0.012935s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1333333332 Hz
[     0.020404s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 666666660/444444440
[     0.027521s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10582010 Hz
[     0.033970s]  INFO(szl): decompressing payload
[     0.040868s] ERROR(szl): LZMA error: LZMA data is corrupt
[     0.046251s] ERROR(szl): decompression failed
[f0697c3ec3](https://git.m-labs.hk/M-Labs/zc706/commit/f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f) does not work. ```patch diff --git a/src/Cargo.lock b/src/Cargo.lock index 138023f..90701c2 100644 --- a/src/Cargo.lock +++ b/src/Cargo.lock @@ -200,7 +200,7 @@ dependencies = [ [[package]] name = "libasync" version = "0.0.0" -source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908" +source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f" dependencies = [ "embedded-hal", "libcortex_a9", @@ -212,7 +212,7 @@ dependencies = [ [[package]] name = "libboard_zynq" version = "0.0.0" -source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908" +source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f" dependencies = [ "bit_field", "embedded-hal", @@ -236,7 +236,7 @@ dependencies = [ [[package]] name = "libcortex_a9" version = "0.0.0" -source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908" +source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f" dependencies = [ "bit_field", "libregister", @@ -245,7 +245,7 @@ dependencies = [ [[package]] name = "libregister" version = "0.0.0" -source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908" +source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f" dependencies = [ "bit_field", "vcell", @@ -255,7 +255,7 @@ dependencies = [ [[package]] name = "libsupport_zynq" version = "0.0.0" -source = "git+https://git.m-labs.hk/M-Labs/zc706.git#6195ad40c334a847cd01cd4adadf6b8f8d730908" +source = "git+https://git.m-labs.hk/M-Labs/zc706.git#f0697c3ec3a40736aabb8ab7d7cf57e8ee52978f" dependencies = [ "compiler_builtins", "libboard_zynq", diff --git a/src/szl/src/main.rs b/src/szl/src/main.rs index 56d0ea8..46e7c8d 100644 --- a/src/szl/src/main.rs +++ b/src/szl/src/main.rs @@ -12,7 +12,6 @@ use libcortex_a9::cache::dcci_slice; use libboard_zynq::{ self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll}, logger, - ps7_init, timer::GlobalTimer, }; use libsupport_zynq as _; @@ -30,12 +29,11 @@ extern fn lzma_error(message: *const u8) { #[no_mangle] pub fn main_core0() { - ps7_init::apply(); - GlobalTimer::start(); logger::init().unwrap(); log::set_max_level(log::LevelFilter::Debug); info!("Simple Zynq Loader starting..."); + info!("NO PS7 INIT!"); unsafe { llvm_asm!(" ``` Still memory corrupted: ``` [ 0.000002s] INFO(szl): Simple Zynq Loader starting... [ 0.005790s] INFO(szl): NO PS7 INIT! [ 0.009443s] INFO(szl): FPU enabled on Core0 [ 0.013792s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 1600000000 Hz [ 0.005714s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz [ 0.012935s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1333333332 Hz [ 0.020404s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 666666660/444444440 [ 0.027521s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10582010 Hz [ 0.033970s] INFO(szl): decompressing payload [ 0.040868s] ERROR(szl): LZMA error: LZMA data is corrupt [ 0.046251s] ERROR(szl): decompression failed ```
sb10q commented 2020-07-05 21:01:12 +08:00
Poster
Owner 
pub const INIT_DATA: &'static [InitOp] = &[
    MaskWrite(0xF8006014, 0x1FFFFF, 0x4159B),
    MaskWrite(0xF800601C, 0xFFFFFFFF, 0x720238E5),
    MaskWrite(0xF8006030, 0xFFFFFFFF, 0x40930),
    MaskWrite(0xF8006050, 0xFF0F8FFF, 0x77010800),
    MaskWrite(0xF80060B0, 0x1FFFFFFF, 0x1CFFFFFF),
    MaskWrite(0xF80060B8, 0x1FFFFFF, 0x200066),
    MaskWrite(0xF8006138, 0xFFFFF, 0x3B821),
    MaskWrite(0xF8006194, 0xFFFFF, 0x1FC82),
];

Confirmed that this seems sufficient to fix the SDRAM. But having only these writes seems to break (I guess) the PS/PL interface; the firmware freezes right before INFO(runtime): detected gateware: Simple (it does not print it).

> ```rust > pub const INIT_DATA: &'static [InitOp] = &[ > MaskWrite(0xF8006014, 0x1FFFFF, 0x4159B), > MaskWrite(0xF800601C, 0xFFFFFFFF, 0x720238E5), > MaskWrite(0xF8006030, 0xFFFFFFFF, 0x40930), > MaskWrite(0xF8006050, 0xFF0F8FFF, 0x77010800), > MaskWrite(0xF80060B0, 0x1FFFFFFF, 0x1CFFFFFF), > MaskWrite(0xF80060B8, 0x1FFFFFF, 0x200066), > MaskWrite(0xF8006138, 0xFFFFF, 0x3B821), > MaskWrite(0xF8006194, 0xFFFFF, 0x1FC82), > ]; > > ``` Confirmed that this seems sufficient to fix the SDRAM. But having only these writes seems to break (I guess) the PS/PL interface; the firmware freezes right before ``INFO(runtime): detected gateware: Simple`` (it does not print it).
sb10q commented 2020-07-06 00:42:33 +08:00
Poster
Owner

Adding the "ps7_post_config_3_0" operations makes the PS/PL interface work.

Adding the "ps7_post_config_3_0" operations makes the PS/PL interface work.
sb10q commented 2020-07-06 00:53:47 +08:00
Poster
Owner

Or just call slcr.init_postload_fpga() :)

Or just call ``slcr.init_postload_fpga()`` :)
sb10q commented 2020-07-06 22:09:21 +08:00
Poster
Owner

Looks resolved now.

Looks resolved now.
sb10q closed this issue 2020-07-06 22:09:26 +08:00
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Reference: M-Labs/artiq-zynq#5
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