Master sends EchoReply for unknown reasons #344

New Issue

mwojcik · 2024-11-29T15:52:38+08:00

mwojcik commented

2024-11-29 15:52:38 +08:00

#322 seemed to touch on the topic before, but it was a different issue causing the timeouts with 2 satellites.

As described in https://forum.m-labs.hk/d/775-destn-communication-failed-timed-out-with-artiq8-zynq

Reproduced with Kasli-SoC master and both 2.0 and SoC satellite by @srenblad

Happens exactly with self.core.wait_until_mu(now_mu()) running.

Since that is a loop that is constantly reading the RTIO counter from CSR, it seems like there may be a conflict and data on the AXI/CSR bus may be incorrect, when read/written by two cores at the same time.

#322 seemed to touch on the topic before, but it was a different issue causing the timeouts with 2 satellites. As described in https://forum.m-labs.hk/d/775-destn-communication-failed-timed-out-with-artiq8-zynq Reproduced with Kasli-SoC master and both 2.0 and SoC satellite by @srenblad Happens exactly with ``self.core.wait_until_mu(now_mu())`` running. Since that is a loop that is constantly reading the RTIO counter from CSR, it seems like there may be a conflict and data on the AXI/CSR bus may be incorrect, when read/written by two cores at the same time.

srenblad commented

2024-11-29 16:12:05 +08:00

Not relevant for configs with Kasli v2 as master.