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FIQ: custom handler not working on master but works fine on satman #287

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opened 2024-03-04 12:22:14 +08:00 by morgan · 1 comment
morgan commented 2024-03-04 12:22:14 +08:00
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Summary

After compiling a custom FIQ handler with the latest zynq-rs, master still run the "dummy fiq handler" instead of the custom one.
Also, if a custom FIQ handler is not provided at artiq-zynq, the compiler will complain about the missing FIQ function

However, satman will enter the custom FIQ handler no problem. And not tested on standalone.

Related PR

Error log

  • when custom FIQ handler is removed
error: linking with `rust-lld` failed: exit code: 1
  |
  = note: "rust-lld" "-flavor" "gnu" "--eh-frame-hdr" "-L" "/build/src/runtime/../../build/sysroot/lib/rustlib/armv7-none-eabihf/lib" "/build/src/runtime/../../build/f>
  = note: '+vfp2d16' is not a recognized feature for this target (ignoring feature)
          '+vfp2d16sp' is not a recognized feature for this target (ignoring feature)
          '+vfp2d16' is not a recognized feature for this target (ignoring feature)
          '+vfp2d16sp' is not a recognized feature for this target (ignoring feature)
          rust-lld: error: undefined symbol: FIQ
          >>> referenced by runtime.6zyso91l-cgu.0
          >>>               /build/src/runtime/../../build/firmware/armv7-none-eabihf/release/deps/runtime-9d96dc3347ac28db.runtime.6zyso91l-cgu.0.rcgu.o:(.text.except>
          

error: aborting due to previous error; 1 warning emitted

error: could not compile `runtime`

To learn more, run the command again with --verbose.
make: *** [Makefile:24: ../build/firmware/armv7-none-eabihf/release/runtime] Error 101

UART log

                     __________   __
                    / ___/__  /  / /
                    \__ \  / /  / /
                   ___/ / / /__/ /___
                  /____/ /____/_____/

                 (C) 2020-2022 M-Labs

[     0.019992s]  INFO(szl): Simple Zynq Loader starting...
[     0.025199s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 2000000000 Hz
[     0.007040s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz
[     0.016259s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1066666666 Hz
[     0.023608s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 533333328/355555552
[     0.030771s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10062892 Hz (divisors=2*53)
[     0.042000s] DEBUG(libboard_zynq::sdio): Reset SDIO!
[     0.046947s] DEBUG(libboard_zynq::sdio): Changing clock frequency to 400000
[     0.053895s]  INFO(szl): No SD card inserted.
[     0.058232s]  INFO(szl::netboot): Preparing network for netboot
[     0.069334s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     0.101035s]  INFO(szl::netboot): Network addresses: MAC=68-27-19-b4-f1-62 IPv4=192.168.1.56 
[     0.109607s] DEBUG(libboard_zynq::eth): Eth TX clock for 125000000: 999999990 / 1 / 8 = 124999998
[     0.130119s]  INFO(szl::netboot): Waiting for connections...
[     5.011374s]  INFO(szl::netboot): Received firmware load command
[     5.062148s]  INFO(szl::netboot): Firmware successfully downloaded
[     5.071129s]  INFO(szl::netboot): Received gateware load command
[     5.193035s]  INFO(szl::netboot): Preprocessing bitstream...
[     5.225111s] DEBUG(libboard_zynq::devc): Invalidate DCache for bitstream buffer
[     5.237978s] DEBUG(libboard_zynq::devc): Init preload FPGA
[     5.243446s] DEBUG(libboard_zynq::devc): Toggling PROG_B
[     5.270877s] DEBUG(libboard_zynq::devc): Waiting for done
[     5.276258s] DEBUG(libboard_zynq::devc): Init postload FPGA
[     5.281812s]  INFO(szl::netboot): Gateware successfully downloaded
[     5.287975s]  INFO(szl::netboot): Received boot command
[     5.293205s]  INFO(szl): Preparing for runtime execution
[     5.298837s]  INFO(szl): executing payload
[     0.000067s]  INFO(runtime): NAR3/Zynq7000 starting...
[     0.005245s]  INFO(runtime): gateware ident: master
[     0.015300s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     0.168004s]  WARN(runtime): config initialization failed: SD error: Card initialization error: No card inserted, check if the card is inserted properly.
[     0.181726s]  WARN(runtime::rtio_clocking): error reading configuration. Falling back to default.
[     0.190579s]  WARN(runtime::rtio_clocking): Using default configuration - internal 125MHz RTIO clock.
[     0.199780s]  INFO(runtime::rtio_clocking): using internal 125MHz RTIO clock
[     0.396377s]  INFO(libboard_artiq::si549): Main Si549 started
[     0.589455s]  INFO(libboard_artiq::si549::wrpll): Helper Si549 started
[     5.646989s]  INFO(runtime::rtio_clocking): SYS CLK switched successfully
[     5.653765s]  INFO(libboard_artiq::si549::wrpll): warming up refclk...
[     5.810480s]  INFO(libboard_artiq::si549::wrpll): KP = 6, KI = 2
[     5.816469s]  INFO(libboard_artiq::si549::wrpll): adding 0ppm to main & helper base adpll (-63496)
[     5.825409s]  INFO(libboard_artiq::si549::wrpll): ref tag = 654514059 
[     5.831919s]  INFO(libboard_artiq::si549::wrpll): main tag = 655320333 
FIQ hello from zynq-rs
## Summary After compiling a custom FIQ handler with the latest zynq-rs, master still run the "dummy fiq handler" instead of the custom one. Also, if a custom FIQ handler is not provided at artiq-zynq, the compiler will complain about the missing FIQ function However, satman will enter the custom FIQ handler no problem. And not tested on standalone. ## Related PR - [zynq-rs/109](https://git.m-labs.hk/M-Labs/zynq-rs/pulls/109) - [zynq-rs/110](https://git.m-labs.hk/M-Labs/zynq-rs/pulls/110) ## Error log - when custom FIQ handler is removed ```bash error: linking with `rust-lld` failed: exit code: 1 | = note: "rust-lld" "-flavor" "gnu" "--eh-frame-hdr" "-L" "/build/src/runtime/../../build/sysroot/lib/rustlib/armv7-none-eabihf/lib" "/build/src/runtime/../../build/f> = note: '+vfp2d16' is not a recognized feature for this target (ignoring feature) '+vfp2d16sp' is not a recognized feature for this target (ignoring feature) '+vfp2d16' is not a recognized feature for this target (ignoring feature) '+vfp2d16sp' is not a recognized feature for this target (ignoring feature) rust-lld: error: undefined symbol: FIQ >>> referenced by runtime.6zyso91l-cgu.0 >>> /build/src/runtime/../../build/firmware/armv7-none-eabihf/release/deps/runtime-9d96dc3347ac28db.runtime.6zyso91l-cgu.0.rcgu.o:(.text.except> error: aborting due to previous error; 1 warning emitted error: could not compile `runtime` To learn more, run the command again with --verbose. make: *** [Makefile:24: ../build/firmware/armv7-none-eabihf/release/runtime] Error 101 ``` ## UART log - [WRPLL dev artiq-zynq repo](https://git.m-labs.hk/morgan/artiq-zynq/src/branch/fiq_issue) & [modified zynq-rs repo](https://git.m-labs.hk/morgan/zynq-rs/src/branch/fiq_issue) with a `println!("FIQ hello from zynq-rs")` at the dummy FIQ handler are compiled together ```bash __________ __ / ___/__ / / / \__ \ / / / / ___/ / / /__/ /___ /____/ /____/_____/ (C) 2020-2022 M-Labs [ 0.019992s] INFO(szl): Simple Zynq Loader starting... [ 0.025199s] DEBUG(libboard_zynq::clocks::source): Set ARM_PLL to 2000000000 Hz [ 0.007040s] DEBUG(libboard_zynq::clocks::source): Set IO_PLL to 1000000000 Hz [ 0.016259s] DEBUG(libboard_zynq::clocks::source): Set DDR_PLL to 1066666666 Hz [ 0.023608s] DEBUG(libboard_zynq::ddr): DDR 3x/2x clocks: 533333328/355555552 [ 0.030771s] DEBUG(libboard_zynq::ddr): DDR DCI clock: 10062892 Hz (divisors=2*53) [ 0.042000s] DEBUG(libboard_zynq::sdio): Reset SDIO! [ 0.046947s] DEBUG(libboard_zynq::sdio): Changing clock frequency to 400000 [ 0.053895s] INFO(szl): No SD card inserted. [ 0.058232s] INFO(szl::netboot): Preparing network for netboot [ 0.069334s] INFO(libboard_zynq::i2c): PCA9548 detected [ 0.101035s] INFO(szl::netboot): Network addresses: MAC=68-27-19-b4-f1-62 IPv4=192.168.1.56 [ 0.109607s] DEBUG(libboard_zynq::eth): Eth TX clock for 125000000: 999999990 / 1 / 8 = 124999998 [ 0.130119s] INFO(szl::netboot): Waiting for connections... [ 5.011374s] INFO(szl::netboot): Received firmware load command [ 5.062148s] INFO(szl::netboot): Firmware successfully downloaded [ 5.071129s] INFO(szl::netboot): Received gateware load command [ 5.193035s] INFO(szl::netboot): Preprocessing bitstream... [ 5.225111s] DEBUG(libboard_zynq::devc): Invalidate DCache for bitstream buffer [ 5.237978s] DEBUG(libboard_zynq::devc): Init preload FPGA [ 5.243446s] DEBUG(libboard_zynq::devc): Toggling PROG_B [ 5.270877s] DEBUG(libboard_zynq::devc): Waiting for done [ 5.276258s] DEBUG(libboard_zynq::devc): Init postload FPGA [ 5.281812s] INFO(szl::netboot): Gateware successfully downloaded [ 5.287975s] INFO(szl::netboot): Received boot command [ 5.293205s] INFO(szl): Preparing for runtime execution [ 5.298837s] INFO(szl): executing payload [ 0.000067s] INFO(runtime): NAR3/Zynq7000 starting... [ 0.005245s] INFO(runtime): gateware ident: master [ 0.015300s] INFO(libboard_zynq::i2c): PCA9548 detected [ 0.168004s] WARN(runtime): config initialization failed: SD error: Card initialization error: No card inserted, check if the card is inserted properly. [ 0.181726s] WARN(runtime::rtio_clocking): error reading configuration. Falling back to default. [ 0.190579s] WARN(runtime::rtio_clocking): Using default configuration - internal 125MHz RTIO clock. [ 0.199780s] INFO(runtime::rtio_clocking): using internal 125MHz RTIO clock [ 0.396377s] INFO(libboard_artiq::si549): Main Si549 started [ 0.589455s] INFO(libboard_artiq::si549::wrpll): Helper Si549 started [ 5.646989s] INFO(runtime::rtio_clocking): SYS CLK switched successfully [ 5.653765s] INFO(libboard_artiq::si549::wrpll): warming up refclk... [ 5.810480s] INFO(libboard_artiq::si549::wrpll): KP = 6, KI = 2 [ 5.816469s] INFO(libboard_artiq::si549::wrpll): adding 0ppm to main & helper base adpll (-63496) [ 5.825409s] INFO(libboard_artiq::si549::wrpll): ref tag = 654514059 [ 5.831919s] INFO(libboard_artiq::si549::wrpll): main tag = 655320333 FIQ hello from zynq-rs ```
sb10q commented 2024-03-04 14:36:05 +08:00
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I suspect Rust feature flags need to be passed across crate dependencies. Probably this is currently not done properly and you end up with several versions of zynq-rs (or its constituent crates) with different feature flags.

I suspect Rust feature flags need to be passed across crate dependencies. Probably this is currently not done properly and you end up with several versions of zynq-rs (or its constituent crates) with different feature flags.
sb10q closed this issue 2024-03-07 15:42:32 +08:00
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