ZC706+Evaluation Board Not Running Idle Kernels #204

Closed
opened 2022-10-25 23:52:44 +08:00 by jfniedermeyer · 6 comments

Bug Report

One-Line Summary

Zynq ZC706+Evaluation Board will not run idle kernels.

Issue Details

Steps to Reproduce

  1. Flash Zynq ZC706+Evaluation Board with zc706-nist_qc2-sd:134016
  2. Build simple idle kernel .py file, such as turning on a output TTL.
  3. Use artiq_compile to build .elf file and artiq_coremgmt to write .elf to the core.
  4. Terminate all other exeriments and look for the idle kernel to run.

Expected Behavior

Idle kernel runs on the core when no other experiments are running.

Actual (undesired) Behavior

  • Idle kernel does not run. No error messages or logs indicating that it tries to run. Also observed by @ljstephenson.

Your System (omit irrelevant parts)

  • Operating System: Windows 10
  • ARTIQ version: ARTIQ v7.8116.eba143a
  • Version of the gateware and runtime loaded in the core device: consistent with build 134016 and commit a3ae8250c
  • See attached conda list
  • Hardware involved: ZC706+Evaluation Board
# Bug Report <!-- Thanks for reporting a bug report to ARTIQ! You can also discuss issues and ask questions on IRC (the [#m-labs channel on freenode](https://webchat.freenode.net/?channels=m-labs) or on the [forum](https://forum.m-labs.hk). Please check Github/those forums to avoid posting a repeat issue. Context helps us fix issues faster, so please include the following when relevant: --> ## One-Line Summary Zynq ZC706+Evaluation Board will not run idle kernels. ## Issue Details ### Steps to Reproduce 1. Flash Zynq ZC706+Evaluation Board with `zc706-nist_qc2-sd:134016` 2. Build simple idle kernel .py file, such as turning on a output TTL. 3. Use `artiq_compile` to build .elf file and `artiq_coremgmt` to write .elf to the core. 4. Terminate all other exeriments and look for the idle kernel to run. ### Expected Behavior Idle kernel runs on the core when no other experiments are running. ### Actual (undesired) Behavior * Idle kernel does not run. No error messages or logs indicating that it tries to run. Also observed by @ljstephenson. ### Your System (omit irrelevant parts) * Operating System: Windows 10 * ARTIQ version: `ARTIQ v7.8116.eba143a` * Version of the gateware and runtime loaded in the core device: consistent with build 134016 and commit a3ae8250c * See attached conda list * Hardware involved: ZC706+Evaluation Board <!-- For in-depth information on bug reporting, see: http://www.chiark.greenend.org.uk/~sgtatham/bugs.html https://developer.mozilla.org/en-US/docs/Mozilla/QA/Bug_writing_guidelines -->
esavkin was assigned by sb10q 2022-10-27 21:22:02 +08:00

@esavkin try it on Kasli-SoC, it's the same code.

@esavkin try it on Kasli-SoC, it's the same code.

Can confirm it reproduces as in the description.
However, idle kernel can be run, but after board's reboot. Also, there is (possibly mistaken) difference from documentation and RISC-V ARTIQ - the config key is idle instead of idle_kernel.
So the command would be like this:

$ artiq_coremgmt config write -f idle examples/blink_forever.elf

@sb10q which one of these is the bug to be fixed?

Can confirm it reproduces as in the description. However, idle kernel can be run, but after board's reboot. Also, there is (possibly mistaken) difference from documentation and RISC-V ARTIQ - the config key is `idle` instead of `idle_kernel`. So the command would be like this: ```sh $ artiq_coremgmt config write -f idle examples/blink_forever.elf ``` @sb10q which one of these is the bug to be fixed?

Ah, that's easy then. Just rename the config key in the artiq-zynq code to follow RISC-V.

RISC-V might also require a reboot to run idle kernels, check if that is the case. Probably mentioning the reboot - if required - in the documentation would be good.

Ah, that's easy then. Just rename the config key in the artiq-zynq code to follow RISC-V. RISC-V might also require a reboot to run idle kernels, check if that is the case. Probably mentioning the reboot - if required - in the documentation would be good.

RISC-V version doesn't require reboot. It needs to run experiment only

RISC-V version doesn't require reboot. It needs to run experiment only

It needs to run experiment only

Well, that's pretty silly behavior. Maybe modify it to require reboot to align with Zynq, and then document.

> It needs to run experiment only Well, that's pretty silly behavior. Maybe modify it to require reboot to align with Zynq, and then document.

Well, that's pretty silly behavior. Maybe modify it to require reboot to align with Zynq, and then document.

https://github.com/m-labs/artiq/issues/2041

> Well, that's pretty silly behavior. Maybe modify it to require reboot to align with Zynq, and then document. https://github.com/m-labs/artiq/issues/2041
sb10q closed this issue 2023-01-03 11:03:11 +08:00
Sign in to join this conversation.
No Milestone
No Assignees
3 Participants
Notifications
Due Date
The due date is invalid or out of range. Please use the format 'yyyy-mm-dd'.

No due date set.

Dependencies

No dependencies set.

Reference: M-Labs/artiq-zynq#204
There is no content yet.