M-Labs/artiq-zynq
10
1
Fork 19
Code Issues 12 Pull Requests Releases Wiki Activity

Problem with sampler on Kasli-Soc #197

New Issue
Closed
opened 2022-08-24 15:16:51 +08:00 by kk105 · 12 comments
kk105 commented 2022-08-24 15:16:51 +08:00
Contributor
Copy Link

When the sampler is connected to the EEM2&3,3&4 and 4&5, the sampler test will fail. But the sampler test can pass for the other EEM ports. This has been reproduced with two independent sets of boards.

When the sampler is connected to the EEM2&3,3&4 and 4&5, the sampler test will fail. But the sampler test can pass for the other EEM ports. This has been reproduced with two independent sets of boards.
esavkin commented 2023-02-14 17:43:21 +08:00
Owner
Copy Link

We came across similar issue during our tests, but we need further investigation, as there were issues with EEM6&7 ports too. The system consists of Kasli-Soc, SMA-TTL and Zotino.
Here is our test log:

Testing:  sampler0
Apply 1.5V to channel 0. Press ENTER when done.

FAILED
-9.2 0.0 10.0 0.0 -0.0 0.0 0.0 -0.0
Apply 1.5V to channel 1. Press ENTER when done.

FAILED
10.0 0.8 -0.0 0.0 -0.0 0.0 -10.0 -0.0
Apply 1.5V to channel 2. Press ENTER when done.

FAILED
10.0 0.0 -9.2 0.0 -0.0 0.0 -0.0 -0.0
Apply 1.5V to channel 3. Press ENTER when done.

FAILED
-0.0 0.0 -10.0 0.8 -0.0 0.0 -10.0 -0.0
Apply 1.5V to channel 4. Press ENTER when done.

FAILED
-0.0 0.0 -0.0 0.0 -9.2 0.0 0.0 -0.0
Apply 1.5V to channel 5. Press ENTER when done.

FAILED
10.0 0.0 10.0 0.0 -10.0 0.8 0.0 -0.0
Apply 1.5V to channel 6. Press ENTER when done.

FAILED
0.0 0.0 10.0 0.0 -0.0 0.0 0.8 -0.0
Apply 1.5V to channel 7. Press ENTER when done.

FAILED
10.0 0.0 10.0 0.0 10.0 0.0 0.0 0.8
We came across similar issue during our tests, but we need further investigation, as there were issues with EEM6&7 ports too. The system consists of Kasli-Soc, SMA-TTL and Zotino. Here is our test log: ``` Testing: sampler0 Apply 1.5V to channel 0. Press ENTER when done. FAILED -9.2 0.0 10.0 0.0 -0.0 0.0 0.0 -0.0 Apply 1.5V to channel 1. Press ENTER when done. FAILED 10.0 0.8 -0.0 0.0 -0.0 0.0 -10.0 -0.0 Apply 1.5V to channel 2. Press ENTER when done. FAILED 10.0 0.0 -9.2 0.0 -0.0 0.0 -0.0 -0.0 Apply 1.5V to channel 3. Press ENTER when done. FAILED -0.0 0.0 -10.0 0.8 -0.0 0.0 -10.0 -0.0 Apply 1.5V to channel 4. Press ENTER when done. FAILED -0.0 0.0 -0.0 0.0 -9.2 0.0 0.0 -0.0 Apply 1.5V to channel 5. Press ENTER when done. FAILED 10.0 0.0 10.0 0.0 -10.0 0.8 0.0 -0.0 Apply 1.5V to channel 6. Press ENTER when done. FAILED 0.0 0.0 10.0 0.0 -0.0 0.0 0.8 -0.0 Apply 1.5V to channel 7. Press ENTER when done. FAILED 10.0 0.0 10.0 0.0 10.0 0.0 0.0 0.8 ```
esavkin commented 2023-02-15 11:59:46 +08:00
Owner
Copy Link

Tested another Kasli-SoC, can confirm the issue persists for 2&3, 4&5, 6&7 EEM ports.

Tested another Kasli-SoC, can confirm the issue persists for 2&3, 4&5, 6&7 EEM ports.
esavkin commented 2023-02-28 16:59:55 +08:00
Owner
Copy Link

Quite possibly there is similar problem for the Mirny, as we came across it with failure ValueError: Mirny PROTO_REV mismatch. Also 9&10 EEM channels didn't work out for Sampler

Quite possibly there is similar problem for the Mirny, as we came across it with failure `ValueError: Mirny PROTO_REV mismatch`. Also 9&10 EEM channels didn't work out for Sampler
mwojcik commented 2023-02-28 20:55:20 +08:00
Owner
Copy Link

IIRC both Mirny and Sampler use SPI for communication, seems like a common point...

IIRC both Mirny and Sampler use SPI for communication, seems like a common point...
SingularitySurfer commented 2023-04-25 17:33:35 +08:00
Owner
Copy Link

Ports 10&11 also do not work for Sampler right now. The only ports I can confirm working are 8&9.

Ports 10&11 also do not work for Sampler right now. The only ports I can confirm working are 8&9.
sb10q commented 2023-04-25 17:43:18 +08:00
Owner
Copy Link

It could be quite random and be essentially a FPGA timing issue that depends on global P&R results and not just the EEM port numbers. Maybe looking at the signals on the scope when it fails, and IOB packing and timing reports from FPGA compilation could shed some light on what is going on.

It could be quite random and be essentially a FPGA timing issue that depends on global P&R results and not just the EEM port numbers. Maybe looking at the signals on the scope when it fails, and IOB packing and timing reports from FPGA compilation could shed some light on what is going on.
esavkin commented 2023-05-04 13:08:42 +08:00
Owner
Copy Link

I've checked the difference between configurations with failing and not failing sampler (just different ports), and failing configuration produces this additional warning in Vivado IDE in DRC report:

LVDS #1 Warning The following port(s) use the LVDS I/O standard and have bi-directional differential usage. Please note that LVDS is a fixed impedance structure optimized to 100ohm differential. This is only intended to be used in point-to-point transmissions that do not have turn around timing requirements. If the intended usage is a bus structure, please use BLVDS/BLVDS_25, instead. sampler2_adc_spi_n_miso, sampler2_adc_spi_p_miso, sampler2_cnv_n, sampler2_cnv_p, sampler2_pgia_spi_n_miso, sampler2_pgia_spi_n_mosi, sampler2_pgia_spi_p_miso, sampler2_pgia_spi_p_mosi.

Is that much meaningful?

I've checked the difference between configurations with failing and not failing sampler (just different ports), and failing configuration produces this additional warning in Vivado IDE in DRC report: ``` LVDS #1 Warning The following port(s) use the LVDS I/O standard and have bi-directional differential usage. Please note that LVDS is a fixed impedance structure optimized to 100ohm differential. This is only intended to be used in point-to-point transmissions that do not have turn around timing requirements. If the intended usage is a bus structure, please use BLVDS/BLVDS_25, instead. sampler2_adc_spi_n_miso, sampler2_adc_spi_p_miso, sampler2_cnv_n, sampler2_cnv_p, sampler2_pgia_spi_n_miso, sampler2_pgia_spi_n_mosi, sampler2_pgia_spi_p_miso, sampler2_pgia_spi_p_mosi. ``` Is that much meaningful?
esavkin commented 2023-05-05 17:32:42 +08:00
Owner
Copy Link

It looks like the issue is with various LVDS standards used on the Kasli-SoC:

eem_iostandard_dict = {
     0: "LVDS_25",
     1: "LVDS_25",
     2: "LVDS",
     3: "LVDS",
     4: "LVDS",
     5: "LVDS",
     6: "LVDS",
     7: "LVDS",
     8: "LVDS_25",
     9: "LVDS_25",
    10: "LVDS",
    11: "LVDS",
}

While it is all LVDS_25 on RISCV Kasli, on Kasli-SoC the reported EEMs are LVDS_18 standard (p99 https://docs.xilinx.com/v/u/en-US/ug471_7Series_SelectIO). Which as @mwojcik says may be undefined behavior related to clock signal being too low.

It looks like the issue is with various LVDS standards used on the Kasli-SoC: ```py eem_iostandard_dict = { 0: "LVDS_25", 1: "LVDS_25", 2: "LVDS", 3: "LVDS", 4: "LVDS", 5: "LVDS", 6: "LVDS", 7: "LVDS", 8: "LVDS_25", 9: "LVDS_25", 10: "LVDS", 11: "LVDS", } ``` While it is all LVDS_25 on RISCV Kasli, on Kasli-SoC the reported EEMs are LVDS_18 standard (p99 https://docs.xilinx.com/v/u/en-US/ug471_7Series_SelectIO). Which as @mwojcik says may be undefined behavior related to clock signal being too low.
mwojcik commented 2023-06-02 15:55:02 +08:00
Owner
Copy Link

We tested it out more extensively - Sampler (in 1-EEM mode) works exactly only on LVDS_25 pins, but for others gives incorrect values (from a closed set of 10.2, +-5.1, 0.8, +-0.0), if the sampler was actually connected.

However looking at EEM0_0_[PN] (refers to ADC_SCK signal) pins with an oscilloscope from sampler connected to ports 1 and 2 we couldn't see any massive difference in voltage levels of the output.

Maybe it's the input (that is, Sampler's output) that causes problems with this configuration?

We tested it out more extensively - Sampler (in 1-EEM mode) works exactly only on LVDS_25 pins, but for others gives incorrect values (from a closed set of 10.2, +-5.1, 0.8, +-0.0), if the sampler was actually connected. However looking at ``EEM0_0_[PN]`` (refers to ``ADC_SCK`` signal) pins with an oscilloscope from sampler connected to ports 1 and 2 we couldn't see any massive difference in voltage levels of the output. Maybe it's the input (that is, Sampler's output) that causes problems with this configuration?
sb10q commented 2023-06-02 16:40:46 +08:00
Owner
Copy Link

Is DIFF_TERM correctly applied?

Is DIFF_TERM correctly applied?
mwojcik commented 2023-06-02 16:41:43 +08:00
Owner
Copy Link

Funny you mention that, DIFF_TERM was NOT applied for inputs (for outputs they're terminated on the Sampler). I just tested out firmware with DIFF_TERM on ADC_MISO and it seems to work on previously affected ports.

Quick fix, I'll make a PR for mainline ARTIQ.

Funny you mention that, ``DIFF_TERM`` was NOT applied for inputs (for outputs they're terminated on the Sampler). I just tested out firmware with DIFF_TERM on ADC_MISO and it seems to work on previously affected ports. Quick fix, I'll make a PR for mainline ARTIQ.
sb10q commented 2023-06-02 16:43:15 +08:00
Owner
Copy Link

We do need DIFF_TERM on all EEM inputs, so I guess this explains the problem.

We do need DIFF_TERM on all EEM inputs, so I guess this explains the problem.
sb10q closed this issue 2023-06-02 17:22:34 +08:00
Sign in to join this conversation.
No Branch/Tag Specified
Branches Tags
Labels
Clear labels   
priority:critical

   
priority:high

   
priority:low

   
priority:medium
No Label
priority:critical
priority:high
priority:low
priority:medium
Milestone
Clear milestone
No items
No Milestone
Assignees
Clear assignees
No Assignees
5 Participants
Notifications
Due Date
The due date is invalid or out of range. Please use the format 'yyyy-mm-dd'.

No due date set.

Dependencies

No dependencies set.

Reference: M-Labs/artiq-zynq#197
No description provided.
Delete Branch "%!s()"

Deleting a branch is permanent. Although the deleted branch may continue to exist for a short time before it actually gets removed, it CANNOT be undone in most cases. Continue?