zc706 nist_qc2: SPI3 MOSI not working #185

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ljstephenson · 2022-04-16T06:20:20+08:00

ljstephenson commented

2022-04-16 06:20:20 +08:00

With the NIST QC2 gateware, SPI3 MOSI stays at logic low regardless of intended output. CLK and CS output as expected, and MISO reads in properly.

I suspect this is a pin routing issue - haven't looked into the schematics yet but will do as soon as I have time.

In order to debug, I verified that SPI1 worked correctly, as it uses exactly analogous hardware but on the LPC connector. I swapped the hardware to the HPC connector and saw that MOSI stayed low. To exclude (or at least minimize) the possibility of it being a failure on the FPGA, I did the same test with a second zc706 with the same outcome.

I've been seeing this for a while (i.e. multiple gateware versions), but have only recently had the opportunity to debug properly and exclude hardware failure as the cause, so it's entirely possible that this has never worked on zc706.

With the NIST QC2 gateware, SPI3 MOSI stays at logic low regardless of intended output. CLK and CS output as expected, and MISO reads in properly. I suspect this is a pin routing issue - haven't looked into the schematics yet but will do as soon as I have time. In order to debug, I verified that SPI1 worked correctly, as it uses exactly analogous hardware but on the LPC connector. I swapped the hardware to the HPC connector and saw that MOSI stayed low. To exclude (or at least minimize) the possibility of it being a failure on the FPGA, I did the same test with a second zc706 with the same outcome. I've been seeing this for a while (i.e. multiple gateware versions), but have only recently had the opportunity to debug properly and exclude hardware failure as the cause, so it's entirely possible that this has never worked on zc706.

ljstephenson commented

2022-04-16 06:37:17 +08:00

Ah: I think P28 should be R28 here:
https://github.com/m-labs/migen/blob/master/migen/build/platforms/zc706.py#L133

See Page 69, Col. 2:
https://docs.xilinx.com/v/u/en-US/ug954-zc706-eval-board-xc7z045-ap-soc

MOSI of the second SPI channel is LA26_P from https://github.com/m-labs/artiq/blob/master/artiq/gateware/nist_qc2.py#L65

Ah: I think `P28` should be `R28` here: https://github.com/m-labs/migen/blob/master/migen/build/platforms/zc706.py#L133 See Page 69, Col. 2: https://docs.xilinx.com/v/u/en-US/ug954-zc706-eval-board-xc7z045-ap-soc MOSI of the second SPI channel is `LA26_P` from https://github.com/m-labs/artiq/blob/master/artiq/gateware/nist_qc2.py#L65

mwojcik was assigned by sb10q

2022-04-18 16:05:53 +08:00

sb10q closed this issue

2022-04-19 14:31:20 +08:00

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