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review FSBL boot #118

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opened 2021-01-15 11:35:09 +08:00 by sb10q · 8 comments
sb10q commented 2021-01-15 11:35:09 +08:00
Owner
  • FPU enable
  • L2 cache enable
* FPU enable * L2 cache enable
pca006132 commented 2021-01-25 14:00:59 +08:00

It seems that FSBL would enable FPU but the L2 cache is not enabled. Unit tests passed, the performance is not as good as when L2 cache is enabled but should be acceptable...
I wonder if we should enable the L2 cache in artiq-zynq rather than zynq-rs, as I'm not sure what would happen if you enable L2 cache twice...

Another workaround would be to boot szl with FSBL, and use netboot as network bootloader for artiq-zynq. But it may require adding some config for szl to prevent it from loading itself indefinitely.

It seems that FSBL would enable FPU but the L2 cache is not enabled. Unit tests passed, the performance is not as good as when L2 cache is enabled but should be acceptable... I wonder if we should enable the L2 cache in `artiq-zynq` rather than `zynq-rs`, as I'm not sure what would happen if you enable L2 cache twice... Another workaround would be to boot szl with FSBL, and use netboot as network bootloader for `artiq-zynq`. But it may require adding some config for `szl` to prevent it from loading itself indefinitely.
sb10q commented 2021-01-25 16:37:46 +08:00
Poster
Owner

It seems that FSBL would enable FPU

OK, and SZL does the same, and ARTIQ does not re-enable it - correct?

I wonder if we should enable the L2 cache in artiq-zynq rather than zynq-rs

This sounds like the correct solution for FSBL compatibility/consistency.

> It seems that FSBL would enable FPU OK, and SZL does the same, and ARTIQ does not re-enable it - correct? > I wonder if we should enable the L2 cache in artiq-zynq rather than zynq-rs This sounds like the correct solution for FSBL compatibility/consistency.
dpn commented 2021-01-25 16:51:34 +08:00

What's the impetus here? Being able to cross-check with ARTIQ booted from FSBL in case of any issues?

What's the impetus here? Being able to cross-check with ARTIQ booted from FSBL in case of any issues?
pca006132 commented 2021-01-25 16:59:53 +08:00

It seems that FSBL would enable FPU

OK, and SZL does the same, and ARTIQ does not re-enable it - correct?

ARTIQ would re-enable it for core1. Maybe we should just drop that, and enable fpu for both cores in szl.

I wonder if we should enable the L2 cache in artiq-zynq rather than zynq-rs

This sounds like the correct solution for FSBL compatibility/consistency.

OK

What's the impetus here? Being able to cross-check with ARTIQ booted from FSBL in case of any issues?

See #94, currently there are some issues with the RAM initialization for a board, and it has to use FSBL for initialization. Still need some time to fix the issue.

> > It seems that FSBL would enable FPU > > OK, and SZL does the same, and ARTIQ does not re-enable it - correct? ARTIQ would re-enable it for core1. Maybe we should just drop that, and enable fpu for both cores in szl. > > I wonder if we should enable the L2 cache in artiq-zynq rather than zynq-rs > > This sounds like the correct solution for FSBL compatibility/consistency. OK > What's the impetus here? Being able to cross-check with ARTIQ booted from FSBL in case of any issues? See #94, currently there are some issues with the RAM initialization for a board, and it has to use FSBL for initialization. Still need some time to fix the issue.
sb10q commented 2021-01-25 17:08:50 +08:00
Poster
Owner

Maybe we should just drop that, and enable fpu for both cores in szl.

Yes, if FSBL enables it on both cores.

> Maybe we should just drop that, and enable fpu for both cores in szl. Yes, if FSBL enables it on both cores.
sb10q commented 2021-01-25 17:09:32 +08:00
Poster
Owner

What's the impetus here? Being able to cross-check with ARTIQ booted from FSBL in case of any issues?

Also make SZL more general and able to boot non-ARTIQ payloads.

> What's the impetus here? Being able to cross-check with ARTIQ booted from FSBL in case of any issues? Also make SZL more general and able to boot non-ARTIQ payloads.
pca006132 commented 2021-01-25 17:14:06 +08:00

Maybe we should just drop that, and enable fpu for both cores in szl.

Yes, if FSBL enables it on both cores.

Sorry, no.
Currently both FSBL and SZL would not enable fpu on core1.

> > Maybe we should just drop that, and enable fpu for both cores in szl. > > Yes, if FSBL enables it on both cores. Sorry, no. Currently both FSBL and SZL would not enable fpu on core1.
pca006132 commented 2021-01-25 17:25:36 +08:00

Also, apart from L2 cache, SZL would also some CPU options that improves performance. I'm not sure if FSBL would enable those.

E.g. prefetch, branch prediction, etc.

Also, apart from L2 cache, SZL would also some CPU options that improves performance. I'm not sure if FSBL would enable those. E.g. prefetch, branch prediction, etc.
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Reference: M-Labs/artiq-zynq#118
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