Compare commits
No commits in common. "master" and "format-fix" have entirely different histories.
master
...
format-fix
10
README.md
10
README.md
|
@ -59,16 +59,6 @@ Notes:
|
|||
- Firmware type must be either ``runtime`` for DRTIO-less or DRTIO master variants, or ``satman`` for DRTIO satellite.
|
||||
- If the board is connected to the local machine, use the ``local_run.sh`` script.
|
||||
|
||||
Pre-Commit Hooks
|
||||
----------------
|
||||
|
||||
You are strongly recommended to use the provided pre-commit hooks to automatically reformat files and check for non-optimal Rust/C/C++ practices. Run `pre-commit install` to install the hook and `pre-commit` will automatically run `cargo fmt`, `cargo clippy`, and `clang-format` for you.
|
||||
|
||||
Several things to note:
|
||||
|
||||
- If `cargo fmt`, `cargo clippy`, or `clang-format` returns an error, the pre-commit hook will fail. You should fix all errors before trying to commit again.
|
||||
- If `cargo fmt` or `clang-format` reformats some files, the pre-commit hook will also fail. You should review the changes and, if satisfied, try to commit again.
|
||||
|
||||
License
|
||||
-------
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||||
|
||||
|
|
|
@ -1,70 +0,0 @@
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core_addr = "192.168.1.57"
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||||
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||||
device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
|
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"arguments": {
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"host": core_addr,
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"ref_period": 1e-9,
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"target": "cortexa9",
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},
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},
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"core_log": {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr,
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},
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"core_moninj": {
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"type": "controller",
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"host": "::1",
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"port_proxy": 1383,
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"port": 1384,
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"command": "aqctl_moninj_proxy --port-proxy {port_proxy} --port-control {port} --bind {bind} "
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+ core_addr,
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},
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"core_analyzer": {
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"type": "controller",
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"host": "::1",
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"port_proxy": 1385,
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"port": 1386,
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"command": "aqctl_coreanalyzer_proxy --port-proxy {port_proxy} --port-control {port} --bind {bind} "
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+ core_addr,
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},
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"core_cache": {
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"type": "local",
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"module": "artiq.coredevice.cache",
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"class": "CoreCache",
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},
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"core_dma": {"type": "local", "module": "artiq.coredevice.dma", "class": "CoreDMA"},
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"led0": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 0},
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},
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"led1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 1},
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},
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}
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device_db.update(
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spi0={
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 2},
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},
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dds0={
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"type": "local",
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"module": "artiq.coredevice.ad9834",
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"class": "AD9834",
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"arguments": {"spi_device": "spi0"},
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},
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)
|
|
@ -364,8 +364,7 @@
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(board-package-set { target = "zc706"; variant = "acpki_nist_qc2_satellite_100mhz"; }) //
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(board-package-set { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) //
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(board-package-set { target = "kasli_soc"; variant = "master"; json = ./kasli-soc-master.json; }) //
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(board-package-set { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; }) //
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(board-package-set { target = "ebaz4205"; variant = "base"; });
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(board-package-set { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; });
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hydraJobs = packages.x86_64-linux // { inherit zc706-hitl-tests; inherit gateware-sim; inherit fmt-check; };
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|
@ -385,7 +384,6 @@
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artiqpkgs.artiq
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artiqpkgs.vivado
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binutils-arm
|
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pre-commit
|
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];
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XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
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CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include";
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|
|
|
@ -1,32 +0,0 @@
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|||
BasedOnStyle: LLVM
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|
||||
Language: Cpp
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Standard: Cpp11
|
||||
|
||||
AccessModifierOffset: -1
|
||||
AlignEscapedNewlines: Left
|
||||
AlwaysBreakAfterReturnType: None
|
||||
AlwaysBreakTemplateDeclarations: Yes
|
||||
AllowAllParametersOfDeclarationOnNextLine: false
|
||||
AllowShortFunctionsOnASingleLine: Inline
|
||||
BinPackParameters: false
|
||||
BreakBeforeBinaryOperators: NonAssignment
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BreakBeforeTernaryOperators: true
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BreakConstructorInitializers: AfterColon
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BreakInheritanceList: AfterColon
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ColumnLimit: 120
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ConstructorInitializerAllOnOneLineOrOnePerLine: true
|
||||
ContinuationIndentWidth: 4
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||||
DerivePointerAlignment: false
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IndentCaseLabels: true
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||||
IndentPPDirectives: None
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||||
IndentWidth: 4
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||||
MaxEmptyLinesToKeep: 1
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||||
PointerAlignment: Left
|
||||
ReflowComments: true
|
||||
SortIncludes: false
|
||||
SortUsingDeclarations: true
|
||||
SpaceAfterTemplateKeyword: false
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||||
SpacesBeforeTrailingComments: 2
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TabWidth: 4
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||||
UseTab: Never
|
|
@ -1 +0,0 @@
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|||
doc-valid-idents = ["CPython", "NumPy", ".."]
|
|
@ -1,32 +0,0 @@
|
|||
# See https://pre-commit.com for more information
|
||||
# See https://pre-commit.com/hooks.html for more hooks
|
||||
|
||||
default_stages: [commit]
|
||||
|
||||
repos:
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- repo: local
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||||
hooks:
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- id: cargo-fmt
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name: artiq-zynq cargo format
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entry: nix
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||||
language: system
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types: [file, rust]
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pass_filenames: false
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||||
description: Runs cargo fmt on the codebase.
|
||||
args: [develop, -c, cargo, fmt, --manifest-path, src/Cargo.toml, --all]
|
||||
- id: cargo-clippy
|
||||
name: artiq-zynq cargo clippy
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||||
entry: nix
|
||||
language: system
|
||||
types: [file, rust]
|
||||
pass_filenames: false
|
||||
description: Runs cargo clippy on the codebase.
|
||||
args: [develop, -c, cargo, clippy, --manifest-path, src/Cargo.toml, --tests]
|
||||
- repo: https://github.com/pre-commit/mirrors-clang-format
|
||||
rev: v19.1.0
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||||
hooks:
|
||||
- id: clang-format
|
||||
name: artiq-zynq clang-format
|
||||
description: Runs clang-format on the codebase.
|
||||
files: \.(cpp|h|hpp|c)$
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||||
args: [-style=file, -fallback-style=none, -assume-filename=src/.clang-format]
|
|
@ -1,19 +1,23 @@
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|||
#!/usr/bin/env python
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||||
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||||
import argparse
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from operator import itemgetter
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import analyzer
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import dma
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import dds, spi2, ttl_simple
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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from migen import *
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from migen.build.generic_platform import IOStandard, Misc, Pins, Subsignal
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from migen.build.platforms import ebaz4205
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from migen.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from migen_axi.integration.soc_core import SoCCore
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from misoc.interconnect.csr import *
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||||
|
||||
from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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||||
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||||
import dma
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import analyzer
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||||
|
||||
from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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||||
|
||||
_ps = [
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(
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"ps",
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|
@ -79,17 +83,6 @@ _i2c = [
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|||
)
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||||
]
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||||
|
||||
_spi = [
|
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(
|
||||
"spi",
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0,
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Subsignal("clk", Pins("V20")),
|
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Subsignal("mosi", Pins("U20")),
|
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Subsignal("cs_n", Pins("P19")),
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IOStandard("LVCMOS33"),
|
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)
|
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]
|
||||
|
||||
|
||||
class EBAZ4205(SoCCore):
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def __init__(self, rtio_clk=125e6, acpki=False):
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||||
|
@ -104,7 +97,6 @@ class EBAZ4205(SoCCore):
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platform.add_extension(_ps)
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platform.add_extension(_ddr)
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||||
platform.add_extension(_i2c)
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||||
platform.add_extension(_spi)
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||||
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||||
gmii = platform.request("gmii")
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||||
platform.add_period_constraint(gmii.rx_clk, 10)
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||||
|
@ -179,11 +171,6 @@ class EBAZ4205(SoCCore):
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phy = ttl_simple.Output(user_led)
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self.submodules += phy
|
||||
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
print("SPI at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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spi_phy = spi2.SPIMaster(platform.request("spi"))
|
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self.submodules += spi_phy
|
||||
self.rtio_channels.append(rtio.Channel.from_phy(spi_phy, ififo_depth=4))
|
||||
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
|
||||
self.rtio_channels.append(rtio.LogChannel())
|
||||
|
||||
|
@ -225,14 +212,6 @@ class EBAZ4205(SoCCore):
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|||
self.csr_devices.append("rtio_analyzer")
|
||||
|
||||
|
||||
class BASE(EBAZ4205):
|
||||
def __init__(self, rtio_clk, acpki):
|
||||
EBAZ4205.__init__(self, rtio_clk, acpki)
|
||||
|
||||
|
||||
VARIANTS = {cls.__name__.lower(): cls for cls in [BASE]}
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="ARTIQ port to the EBAZ4205 control card of Ebit E9+ BTC miner"
|
||||
|
@ -253,25 +232,11 @@ def main():
|
|||
)
|
||||
parser.add_argument("--rtio-clk", default=125e6, help="RTIO Clock Frequency (Hz)")
|
||||
parser.add_argument(
|
||||
"-V",
|
||||
"--variant",
|
||||
default="base",
|
||||
help="variant: " "[acpki_]base" "(default: %(default)s)",
|
||||
"--acpki", default=False, action="store_true", help="enable ACPKI"
|
||||
)
|
||||
args = parser.parse_args()
|
||||
|
||||
rtio_clk = int(args.rtio_clk)
|
||||
variant = args.variant.lower()
|
||||
acpki = variant.startswith("acpki_")
|
||||
if acpki:
|
||||
variant = variant[6:]
|
||||
|
||||
try:
|
||||
cls = VARIANTS[variant]
|
||||
except KeyError:
|
||||
raise SystemExit("Invalid variant (-V/--variant)")
|
||||
|
||||
soc = cls(rtio_clk=rtio_clk, acpki=acpki)
|
||||
soc = EBAZ4205(rtio_clk=int(args.rtio_clk), acpki=args.acpki)
|
||||
soc.finalize()
|
||||
|
||||
if args.r is not None:
|
||||
|
|
|
@ -255,7 +255,6 @@ pub enum Packet {
|
|||
destination: u8,
|
||||
id: u32,
|
||||
run: bool,
|
||||
timestamp: u64,
|
||||
},
|
||||
SubkernelLoadRunReply {
|
||||
destination: u8,
|
||||
|
@ -515,7 +514,6 @@ impl Packet {
|
|||
destination: reader.read_u8()?,
|
||||
id: reader.read_u32()?,
|
||||
run: reader.read_bool()?,
|
||||
timestamp: reader.read_u64()?,
|
||||
},
|
||||
0xc5 => Packet::SubkernelLoadRunReply {
|
||||
destination: reader.read_u8()?,
|
||||
|
@ -879,14 +877,12 @@ impl Packet {
|
|||
destination,
|
||||
id,
|
||||
run,
|
||||
timestamp,
|
||||
} => {
|
||||
writer.write_u8(0xc4)?;
|
||||
writer.write_u8(source)?;
|
||||
writer.write_u8(destination)?;
|
||||
writer.write_u32(id)?;
|
||||
writer.write_bool(run)?;
|
||||
writer.write_u64(timestamp)?;
|
||||
}
|
||||
Packet::SubkernelLoadRunReply { destination, succeeded } => {
|
||||
writer.write_u8(0xc5)?;
|
||||
|
|
|
@ -81,7 +81,6 @@ pub enum Message {
|
|||
id: u32,
|
||||
destination: u8,
|
||||
run: bool,
|
||||
timestamp: u64,
|
||||
},
|
||||
#[cfg(has_drtio)]
|
||||
SubkernelLoadRunReply {
|
||||
|
|
|
@ -3,7 +3,7 @@ use alloc::vec::Vec;
|
|||
use cslice::CSlice;
|
||||
|
||||
use super::{Message, SubkernelStatus, KERNEL_CHANNEL_0TO1, KERNEL_CHANNEL_1TO0};
|
||||
use crate::{artiq_raise, eh_artiq, rpc::send_args, rtio::now_mu};
|
||||
use crate::{artiq_raise, eh_artiq, rpc::send_args};
|
||||
|
||||
pub extern "C" fn load_run(id: u32, destination: u8, run: bool) {
|
||||
unsafe {
|
||||
|
@ -14,7 +14,6 @@ pub extern "C" fn load_run(id: u32, destination: u8, run: bool) {
|
|||
id: id,
|
||||
destination: destination,
|
||||
run: run,
|
||||
timestamp: now_mu() as u64,
|
||||
});
|
||||
}
|
||||
match unsafe { KERNEL_CHANNEL_0TO1.as_mut().unwrap() }.recv() {
|
||||
|
|
|
@ -405,9 +405,8 @@ async fn handle_run_kernel(
|
|||
id,
|
||||
destination: _,
|
||||
run,
|
||||
timestamp,
|
||||
} => {
|
||||
let succeeded = match subkernel::load(aux_mutex, routing_table, timer, id, run, timestamp).await {
|
||||
let succeeded = match subkernel::load(aux_mutex, routing_table, timer, id, run).await {
|
||||
Ok(()) => true,
|
||||
Err(e) => {
|
||||
error!("Error loading subkernel: {:?}", e);
|
||||
|
|
|
@ -792,7 +792,6 @@ pub mod drtio {
|
|||
id: u32,
|
||||
destination: u8,
|
||||
run: bool,
|
||||
timestamp: u64,
|
||||
) -> Result<(), Error> {
|
||||
let linkno = routing_table.0[destination as usize][0] - 1;
|
||||
let reply = aux_transact(
|
||||
|
@ -804,7 +803,6 @@ pub mod drtio {
|
|||
source: 0,
|
||||
destination: destination,
|
||||
run: run,
|
||||
timestamp,
|
||||
},
|
||||
timer,
|
||||
)
|
||||
|
|
|
@ -100,22 +100,12 @@ pub async fn load(
|
|||
timer: GlobalTimer,
|
||||
id: u32,
|
||||
run: bool,
|
||||
timestamp: u64,
|
||||
) -> Result<(), Error> {
|
||||
if let Some(subkernel) = SUBKERNELS.async_lock().await.get_mut(&id) {
|
||||
if subkernel.state != SubkernelState::Uploaded {
|
||||
return Err(Error::IncorrectState);
|
||||
}
|
||||
drtio::subkernel_load(
|
||||
aux_mutex,
|
||||
routing_table,
|
||||
timer,
|
||||
id,
|
||||
subkernel.destination,
|
||||
run,
|
||||
timestamp,
|
||||
)
|
||||
.await?;
|
||||
drtio::subkernel_load(aux_mutex, routing_table, timer, id, subkernel.destination, run).await?;
|
||||
if run {
|
||||
subkernel.state = SubkernelState::Running;
|
||||
}
|
||||
|
|
|
@ -826,7 +826,6 @@ fn process_aux_packet(
|
|||
destination: _destination,
|
||||
id,
|
||||
run,
|
||||
timestamp,
|
||||
} => {
|
||||
forward!(
|
||||
router,
|
||||
|
@ -845,7 +844,7 @@ fn process_aux_packet(
|
|||
// cannot run kernel while DDMA is running
|
||||
succeeded = false;
|
||||
} else {
|
||||
succeeded |= kernel_manager.run(source, id, timestamp).is_ok();
|
||||
succeeded |= kernel_manager.run(source, id).is_ok();
|
||||
}
|
||||
}
|
||||
router.send(
|
||||
|
|
|
@ -8,7 +8,7 @@ use core_io::{Error as IoError, Write};
|
|||
use cslice::AsCSlice;
|
||||
use dma::{Error as DmaError, Manager as DmaManager};
|
||||
use io::{Cursor, ProtoWrite};
|
||||
use ksupport::{eh_artiq, kernel, rpc, rtio};
|
||||
use ksupport::{eh_artiq, kernel, rpc};
|
||||
use libboard_artiq::{drtio_routing::RoutingTable,
|
||||
drtioaux,
|
||||
drtioaux_proto::{PayloadStatus, MASTER_PAYLOAD_MAX_SIZE},
|
||||
|
@ -349,7 +349,7 @@ impl<'a> Manager<'_> {
|
|||
}
|
||||
}
|
||||
|
||||
pub fn run(&mut self, source: u8, id: u32, timestamp: u64) -> Result<(), Error> {
|
||||
pub fn run(&mut self, source: u8, id: u32) -> Result<(), Error> {
|
||||
if self.session.kernel_state != KernelState::Loaded || self.session.id != id {
|
||||
self.load(id)?;
|
||||
}
|
||||
|
@ -359,7 +359,6 @@ impl<'a> Manager<'_> {
|
|||
csr::cri_con::selected_write(2);
|
||||
}
|
||||
|
||||
rtio::at_mu(timestamp as i64);
|
||||
self.control.tx.send(kernel::Message::StartRequest);
|
||||
Ok(())
|
||||
}
|
||||
|
@ -813,7 +812,6 @@ impl<'a> Manager<'_> {
|
|||
id,
|
||||
destination: sk_destination,
|
||||
run,
|
||||
timestamp,
|
||||
} => {
|
||||
self.session.kernel_state = KernelState::SubkernelAwaitLoad;
|
||||
router.route(
|
||||
|
@ -822,7 +820,6 @@ impl<'a> Manager<'_> {
|
|||
destination: sk_destination,
|
||||
id: id,
|
||||
run: run,
|
||||
timestamp,
|
||||
},
|
||||
routing_table,
|
||||
rank,
|
||||
|
|
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