8 changed files with 84 additions and 102 deletions
--- a/flake.lock
+++ b/flake.lock
@ -11,11 +11,11 @@
        "src-pythonparser": "src-pythonparser"
      },
      "locked": {
-        "lastModified": 1715076061,
-        "narHash": "sha256-R/GQ9PImzChpwHy2t9gOGR4VQmGf9uE2QeukaPu4w9g=",
-        "ref": "refs/heads/master",
-        "rev": "7dff78e849ceab4992df521875f66b5917a7a8ab",
-        "revCount": 8781,
+        "lastModified": 1714013217,
+        "narHash": "sha256-P0pVHTSgAkTYWFPjddcPhufe5oH8mjJAsxG8x8mo4NA=",
+        "ref": "master",
+        "rev": "7204feae1f504e4a1dcd54b95c59e8f36c62b701",
+        "revCount": 8776,
        "type": "git",
        "url": "https://github.com/m-labs/artiq.git"
      },
@ -103,11 +103,11 @@
    "mozilla-overlay_3": {
      "flake": false,
      "locked": {
-        "lastModified": 1704373101,
-        "narHash": "sha256-+gi59LRWRQmwROrmE1E2b3mtocwueCQqZ60CwLG+gbg=",
+        "lastModified": 1695805681,
+        "narHash": "sha256-1ElPLD8eFfnuIk0G52HGGpRtQZ4QPCjChRlEOfkZ5ro=",
        "owner": "mozilla",
        "repo": "nixpkgs-mozilla",
-        "rev": "9b11a87c0cc54e308fa83aac5b4ee1816d5418a2",
+        "rev": "6eabade97bc28d707a8b9d82ad13ef143836736e",
        "type": "github"
      },
      "original": {
@ -118,16 +118,16 @@
    },
    "nixpkgs": {
      "locked": {
-        "lastModified": 1714906307,
-        "narHash": "sha256-UlRZtrCnhPFSJlDQE7M0eyhgvuuHBTe1eJ9N9AQlJQ0=",
+        "lastModified": 1711668574,
+        "narHash": "sha256-u1dfs0ASQIEr1icTVrsKwg2xToIpn7ZXxW3RHfHxshg=",
        "owner": "NixOS",
        "repo": "nixpkgs",
-        "rev": "25865a40d14b3f9cf19f19b924e2ab4069b09588",
+        "rev": "219951b495fc2eac67b1456824cc1ec1fd2ee659",
        "type": "github"
      },
      "original": {
        "owner": "NixOS",
-        "ref": "nixos-unstable",
+        "ref": "nixos-23.11",
        "repo": "nixpkgs",
        "type": "github"
      }
@ -234,11 +234,11 @@
        ]
      },
      "locked": {
-        "lastModified": 1715220163,
-        "narHash": "sha256-XPQVx8dH0hIUZK7qMZGhtjlOVnWxQBgFLhHgipy1Ph0=",
-        "ref": "refs/heads/master",
-        "rev": "731684abb44c3aa21e6a5a7b45bb3ac164f38c86",
-        "revCount": 644,
+        "lastModified": 1711358419,
+        "narHash": "sha256-LzetYaLsnov9pHVWSCTSowXUAXkxemAa61CIMY98xsc=",
+        "ref": "master",
+        "rev": "195a21fe78e4dde1fd705cb2899ab5d2763ae037",
+        "revCount": 643,
        "type": "git",
        "url": "https://git.m-labs.hk/m-labs/zynq-rs"
      },
--- a/flake.nix
+++ b/flake.nix
@ -132,12 +132,12 @@
          pkgs.gnumake
          (pkgs.python3.withPackages(ps: [ ps.jsonschema artiqpkgs.migen migen-axi artiqpkgs.misoc artiqpkgs.artiq ]))
          zynqpkgs.cargo-xbuild
-          pkgs.llvmPackages_14.llvm
-          pkgs.llvmPackages_14.clang-unwrapped
+          pkgs.llvmPackages_9.llvm
+          pkgs.llvmPackages_9.clang-unwrapped
        ];
        buildPhase = ''
          export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
-          export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_14.clang-unwrapped.lib}/lib/clang/14.0.6/include"
+          export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_9.clang-unwrapped.lib}/lib/clang/9.0.1/include"
          export CARGO_HOME=$(mktemp -d cargo-home.XXX)
          export ZYNQ_RS=${zynq-rs}
          make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
@ -370,8 +370,8 @@
      name = "artiq-zynq-dev-shell";
      buildInputs = with pkgs; [
        rust
-        llvmPackages_14.llvm
-        llvmPackages_14.clang-unwrapped
+        llvmPackages_9.llvm
+        llvmPackages_9.clang-unwrapped
        gnumake
        cacert
        zynqpkgs.cargo-xbuild
@ -384,7 +384,7 @@
        binutils-arm
      ];
      XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
-      CLANG_EXTRA_INCLUDE_DIR = "${pkgs.llvmPackages_14.clang-unwrapped.lib}/lib/clang/14.0.6/include";
+      CLANG_EXTRA_INCLUDE_DIR = "${pkgs.llvmPackages_9.clang-unwrapped.lib}/lib/clang/9.0.1/include";
      ZYNQ_RS = "${zynq-rs}";
      OPENOCD_ZYNQ = "${zynq-rs}/openocd";
      SZL = "${zynqpkgs.szl}";
--- a/src/gateware/kasli_soc.py
+++ b/src/gateware/kasli_soc.py
@ -135,7 +135,6 @@ class GenericStandalone(SoCCore):
        ]
        fix_serdes_timing_path(platform)
        self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
-        self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
        self.config["CLOCK_FREQUENCY"] = int(clk_freq)

        self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se_buf)
@ -243,7 +242,6 @@ class GenericMaster(SoCCore):
            pads=data_pads,
            clk_freq=clk_freq)
        self.csr_devices.append("gt_drtio")
-        self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
        self.config["CLOCK_FREQUENCY"] = int(clk_freq)

        txout_buf = Signal()
--- a/src/libboard_artiq/src/drtioaux.rs
+++ b/src/libboard_artiq/src/drtioaux.rs
@ -1,10 +1,9 @@
-use core::slice;
-
 use core_io::{Error as IoError, ErrorKind as IoErrorKind};
 use crc;
 use io::{proto::{ProtoRead, ProtoWrite},
         Cursor};
 use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
+use libcortex_a9::asm::dmb;

 pub use crate::drtioaux_proto::Packet;
 use crate::{drtioaux_proto::Error as ProtocolError, mem::mem::DRTIOAUX_MEM, pl::csr::DRTIOAUX};
@ -57,6 +56,19 @@ pub fn has_rx_error(linkno: u8) -> bool {
    }
 }

+pub fn copy_work_buffer(src: *mut u32, dst: *mut u32, len: isize) {
+    // AXI writes must be 4-byte aligned (drtio proto doesn't care for that),
+    // and AXI burst reads/writes are not implemented yet in gateware
+    // thus the need for a work buffer for transmitting and copying it over
+    unsafe {
+        for i in 0..(len / 4) {
+            *dst.offset(i) = *src.offset(i);
+            //data memory barrier to prevent bursts
+            dmb();
+        }
+    }
+}
+
 fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error>
 where F: FnOnce(&[u8]) -> Result<T, Error> {
    let linkidx = linkno as usize;
@ -64,7 +76,13 @@ where F: FnOnce(&[u8]) -> Result<T, Error> {
        if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
            let read_ptr = (DRTIOAUX[linkidx].aux_read_pointer_read)() as usize;
            let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2 + read_ptr * 0x400) as *mut u32;
-            let result = f(slice::from_raw_parts(ptr as *mut u8, 0x400 as usize));
+            // work buffer to accomodate axi burst reads
+            // buffer at maximum proto packet size, not maximum gateware supported size
+            // to minimize copying time
+            const LEN: usize = 512;
+            let mut buf: [u8; LEN] = [0; LEN];
+            copy_work_buffer(ptr, buf.as_mut_ptr() as *mut u32, LEN as isize);
+            let result = f(&buf);
            (DRTIOAUX[linkidx].aux_rx_present_write)(1);
            Ok(Some(result?))
        } else {
@ -115,7 +133,10 @@ where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
    unsafe {
        while (DRTIOAUX[linkno].aux_tx_read)() != 0 {}
        let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
-        let len = f(slice::from_raw_parts_mut(ptr as *mut u8, 0x400 as usize))?;
+        // work buffer, works with unaligned mem access
+        let mut buf: [u8; 1024] = [0; 1024];
+        let len = f(&mut buf)?;
+        copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize);
        (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
        (DRTIOAUX[linkno].aux_tx_write)(1);
        Ok(())
--- a/src/libboard_artiq/src/drtioaux_async.rs
+++ b/src/libboard_artiq/src/drtioaux_async.rs
@ -1,5 +1,3 @@
-use core::slice;
-
 use core_io::{Error as IoError, ErrorKind as IoErrorKind};
 use crc;
 use io::{proto::{ProtoRead, ProtoWrite},
@ -10,7 +8,7 @@ use nb;
 use void::Void;

 pub use crate::drtioaux_proto::Packet;
-use crate::{drtioaux::{has_rx_error, Error},
+use crate::{drtioaux::{copy_work_buffer, has_rx_error, Error},
            mem::mem::DRTIOAUX_MEM,
            pl::csr::DRTIOAUX};

@ -42,7 +40,13 @@ where F: FnOnce(&[u8]) -> Result<T, Error> {
        if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
            let read_ptr = (DRTIOAUX[linkidx].aux_read_pointer_read)() as usize;
            let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2 + read_ptr * 0x400) as *mut u32;
-            let result = f(slice::from_raw_parts(ptr as *mut u8, 0x400 as usize));
+            // work buffer to accomodate axi burst reads
+            // buffer at maximum proto packet size, not maximum gateware supported size
+            // to minimize required copying time
+            const LEN: usize = 512;
+            let mut buf: [u8; LEN] = [0; LEN];
+            copy_work_buffer(ptr, buf.as_mut_ptr() as *mut u32, LEN as isize);
+            let result = f(&buf);
            (DRTIOAUX[linkidx].aux_rx_present_write)(1);
            Ok(Some(result?))
        } else {
@ -102,7 +106,10 @@ where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
    unsafe {
        let _ = block_async!(tx_ready(linkno)).await;
        let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
-        let len = f(slice::from_raw_parts_mut(ptr as *mut u8, 0x400 as usize))?;
+        // work buffer, works with unaligned mem access
+        let mut buf: [u8; 1024] = [0; 1024];
+        let len = f(&mut buf)?;
+        copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize);
        (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
        (DRTIOAUX[linkno].aux_tx_write)(1);
        Ok(())
--- a/src/libboard_artiq/src/drtioaux_proto.rs
+++ b/src/libboard_artiq/src/drtioaux_proto.rs
@ -1,11 +1,9 @@
 use core_io::{Error as IoError, Read, Write};
 use io::proto::{ProtoRead, ProtoWrite};

-const MAX_PACKET: usize = 1024;
-
 // maximum size of arbitrary payloads
 // used by satellite -> master analyzer, subkernel exceptions
-pub const SAT_PAYLOAD_MAX_SIZE: usize  = /*max size*/MAX_PACKET - /*CRC*/4 - /*packet ID*/1 - /*last*/1 - /*length*/2;
+pub const SAT_PAYLOAD_MAX_SIZE: usize  = /*max size*/512 - /*CRC*/4 - /*packet ID*/1 - /*last*/1 - /*length*/2;
 // used by DDMA, subkernel program data (need to provide extra ID and destination)
 pub const MASTER_PAYLOAD_MAX_SIZE: usize = SAT_PAYLOAD_MAX_SIZE - /*source*/1 - /*destination*/1 - /*ID*/4;

--- a/src/libboard_artiq/src/si549.rs
+++ b/src/libboard_artiq/src/si549.rs
@ -335,44 +335,16 @@ pub mod wrpll {
    const COUNTER_WIDTH: u32 = 24;
    const DIV_WIDTH: u32 = 2;

-    // y[n] = b0*x[n] + b1*x[n-1] + b2*x[n-2] - a1*y[n-1] - a2*y[n-2]
-    struct FilterParameters {
-        pub b0: f64,
-        pub b1: f64,
-        pub b2: f64,
-        pub a1: f64,
-        pub a2: f64,
-    }
-
-    #[cfg(rtio_frequency = "100.0")]
-    const LPF: FilterParameters = FilterParameters {
-        b0: 0.03967479060647884,
-        b1: 0.07934958121295768,
-        b2: 0.03967479060647884,
-        a1: -1.3865593741228928,
-        a2: 0.5452585365488082,
-    };
-
-    #[cfg(rtio_frequency = "125.0")]
-    const LPF: FilterParameters = FilterParameters {
-        b0: 0.07209205036273991,
-        b1: 0.14418410072547982,
-        b2: 0.07209205036273991,
-        a1: -0.6114078511562919,
-        a2: -0.10022394739274834,
-    };
-
-    static mut H_ADPLL1: i32 = 0;
-    static mut H_ADPLL2: i32 = 0;
-    static mut PERIOD_ERR1: i32 = 0;
-    static mut PERIOD_ERR2: i32 = 0;
-
-    static mut M_ADPLL1: i32 = 0;
-    static mut M_ADPLL2: i32 = 0;
-    static mut PHASE_ERR1: i32 = 0;
-    static mut PHASE_ERR2: i32 = 0;
+    const KP: i32 = 6;
+    const KI: i32 = 2;
+    // 4 ppm capture range
+    const ADPLL_LIM: i32 = (4.0 / 0.0001164) as i32;

    static mut BASE_ADPLL: i32 = 0;
+    static mut H_LAST_ADPLL: i32 = 0;
+    static mut LAST_PERIOD_ERR: i32 = 0;
+    static mut M_LAST_ADPLL: i32 = 0;
+    static mut LAST_PHASE_ERR: i32 = 0;

    #[derive(Clone, Copy)]
    pub enum ISR {
@ -500,14 +472,10 @@ pub mod wrpll {

    fn reset_plls(timer: &mut GlobalTimer) -> Result<(), &'static str> {
        unsafe {
-            H_ADPLL1 = 0;
-            H_ADPLL2 = 0;
-            PERIOD_ERR1 = 0;
-            PERIOD_ERR2 = 0;
-            M_ADPLL1 = 0;
-            M_ADPLL2 = 0;
-            PHASE_ERR1 = 0;
-            PHASE_ERR2 = 0;
+            H_LAST_ADPLL = 0;
+            LAST_PERIOD_ERR = 0;
+            M_LAST_ADPLL = 0;
+            LAST_PHASE_ERR = 0;
        }
        set_adpll(i2c::DCXO::Main, 0)?;
        set_adpll(i2c::DCXO::Helper, 0)?;
@ -551,14 +519,11 @@ pub mod wrpll {
    fn helper_pll() -> Result<(), &'static str> {
        let period_err = tag_collector::get_period_error();
        unsafe {
-            let adpll = ((LPF.b0 * period_err as f64) + (LPF.b1 * PERIOD_ERR1 as f64) + (LPF.b2 * PERIOD_ERR2 as f64)
-                - (LPF.a1 * H_ADPLL1 as f64)
-                - (LPF.a2 * H_ADPLL2 as f64)) as i32;
+            // Based on https://hackmd.io/IACbwcOTSt6Adj3_F9bKuw?view#Integral-wind-up-and-output-limiting
+            let adpll = (H_LAST_ADPLL + (KP + KI) * period_err - KP * LAST_PERIOD_ERR).clamp(-ADPLL_LIM, ADPLL_LIM);
            set_adpll(i2c::DCXO::Helper, BASE_ADPLL + adpll)?;
-            H_ADPLL2 = H_ADPLL1;
-            PERIOD_ERR2 = PERIOD_ERR1;
-            H_ADPLL1 = adpll;
-            PERIOD_ERR1 = period_err;
+            H_LAST_ADPLL = adpll;
+            LAST_PERIOD_ERR = period_err;
        };
        Ok(())
    }
@ -566,14 +531,11 @@ pub mod wrpll {
    fn main_pll() -> Result<(), &'static str> {
        let phase_err = tag_collector::get_phase_error();
        unsafe {
-            let adpll = ((LPF.b0 * phase_err as f64) + (LPF.b1 * PHASE_ERR1 as f64) + (LPF.b2 * PHASE_ERR2 as f64)
-                - (LPF.a1 * M_ADPLL1 as f64)
-                - (LPF.a2 * M_ADPLL2 as f64)) as i32;
+            // Based on https://hackmd.io/IACbwcOTSt6Adj3_F9bKuw?view#Integral-wind-up-and-output-limiting
+            let adpll = (M_LAST_ADPLL + (KP + KI) * phase_err - KP * LAST_PHASE_ERR).clamp(-ADPLL_LIM, ADPLL_LIM);
            set_adpll(i2c::DCXO::Main, BASE_ADPLL + adpll)?;
-            M_ADPLL2 = M_ADPLL1;
-            PHASE_ERR2 = PHASE_ERR1;
-            M_ADPLL1 = adpll;
-            PHASE_ERR1 = phase_err;
+            M_LAST_ADPLL = adpll;
+            LAST_PHASE_ERR = phase_err;
        };
        Ok(())
    }
--- a/src/libio/cursor.rs
+++ b/src/libio/cursor.rs
@ -45,10 +45,7 @@ impl<T: AsRef<[u8]>> Read for Cursor<T> {
    fn read(&mut self, buf: &mut [u8]) -> Result<usize, IoError> {
        let data = &self.inner.as_ref()[self.pos..];
        let len = buf.len().min(data.len());
-        // ``copy_from_slice`` generates AXI bursts, use a regular loop instead
-        for i in 0..len {
-            buf[i] = data[i];
-        }
+        buf[..len].copy_from_slice(&data[..len]);
        self.pos += len;
        Ok(len)
    }
@ -58,9 +55,7 @@ impl Write for Cursor<&mut [u8]> {
    fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
        let data = &mut self.inner[self.pos..];
        let len = buf.len().min(data.len());
-        for i in 0..len {
-            data[i] = buf[i];
-        }
+        data[..len].copy_from_slice(&buf[..len]);
        self.pos += len;
        Ok(len)
    }
@ -73,6 +68,7 @@ impl Write for Cursor<&mut [u8]> {

 #[cfg(feature = "alloc")]
 impl Write for Cursor<Vec<u8>> {
+    #[inline]
    fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
        self.inner.extend_from_slice(buf);
        Ok(buf.len())