cursor write revert to memcpy

flake.lock

@@ -229,17 +229,18 @@
         "rust-overlay": "rust-overlay_2"
       },
       "locked": {
-        "lastModified": 1734668221,
+        "lastModified": 1736152520,
-        "narHash": "sha256-X0U2yPmlsD3VLBZQyfWv8qw04Qn0qFWIONJUPPigB0U=",
+        "narHash": "sha256-+NfLPQfqDKZJK7D0RyXF3GM5eWj5QRr/bYDfOaIZi88=",
-        "ref": "refs/heads/master",
+        "ref": "bump_to_llvm14",
-        "rev": "213529cf7a50aa1b2d9ffdf575e3e38202ff9bd6",
+        "rev": "bae8081935b0b936e1468c0ab74ea6610477ad62",
-        "revCount": 666,
+        "revCount": 678,
         "type": "git",
-        "url": "https://git.m-labs.hk/m-labs/zynq-rs"
+        "url": "https://git.m-labs.hk/srenblad/zynq-rs/"
       },
       "original": {
+        "ref": "bump_to_llvm14",
         "type": "git",
-        "url": "https://git.m-labs.hk/m-labs/zynq-rs"
+        "url": "https://git.m-labs.hk/srenblad/zynq-rs/"
       }
     }
   },

flake.nix

@@ -2,7 +2,7 @@
   description = "ARTIQ port to the Zynq-7000 platform";
 
   inputs.artiq.url = git+https://github.com/m-labs/artiq.git;
-  inputs.zynq-rs.url = git+https://git.m-labs.hk/m-labs/zynq-rs;
+  inputs.zynq-rs.url = git+https://git.m-labs.hk/srenblad/zynq-rs/?ref=bump_to_llvm14;
   inputs.zynq-rs.inputs.nixpkgs.follows = "artiq/nixpkgs";
 
   outputs = { self, zynq-rs, artiq }:
@@ -135,13 +135,13 @@
           pkgs.gnumake
           (pkgs.python3.withPackages(ps: [ ps.jsonschema artiqpkgs.migen migen-axi artiqpkgs.misoc artiqpkgs.artiq ]))
           zynqpkgs.cargo-xbuild
-          pkgs.llvmPackages_13.llvm
+          pkgs.llvmPackages_14.llvm
-          pkgs.llvmPackages_13.clang-unwrapped
+          pkgs.llvmPackages_14.clang-unwrapped
         ];
         buildPhase = ''
           export ZYNQ_REV=${zynqRev}
           export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
-          export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_13.clang-unwrapped.lib}/lib/clang/13.0.1/include"
+          export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_14.clang-unwrapped.lib}/lib/clang/14.0.6/include"
           export CARGO_HOME=$(mktemp -d cargo-home.XXX)
           export ZYNQ_RS=${zynq-rs}
           make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
@@ -376,8 +376,8 @@
       name = "artiq-zynq-dev-shell";
       buildInputs = with pkgs; [
         rust
-        llvmPackages_13.llvm
+        llvmPackages_14.llvm
-        llvmPackages_13.clang-unwrapped
+        llvmPackages_14.clang-unwrapped
         gnumake
         cacert
         zynqpkgs.cargo-xbuild
@@ -392,7 +392,7 @@
       ];
       ZYNQ_REV="${zynqRev}";
       XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
-      CLANG_EXTRA_INCLUDE_DIR = "${pkgs.llvmPackages_13.clang-unwrapped.lib}/lib/clang/13.0.1/include";
+      CLANG_EXTRA_INCLUDE_DIR = "${pkgs.llvmPackages_14.clang-unwrapped.lib}/lib/clang/14.0.6/include";
       ZYNQ_RS = "${zynq-rs}";
       OPENOCD_ZYNQ = "${zynq-rs}/openocd";
       SZL = "${zynqpkgs.szl}";

src/.cargo/config

@@ -1,7 +1,7 @@
 [target.armv7-none-eabihf]
 rustflags = [
   "-C", "link-arg=-Tlink.x",
-  "-C", "target-feature=a9,armv7-a,neon",
+  "-C", "target-feature=+a9,+armv7-a,+neon",
   "-C", "target-cpu=cortex-a9",
 ]
 

src/Cargo.lock

@@ -82,9 +82,9 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
 
 [[package]]
 name = "compiler_builtins"
-version = "0.1.49"
+version = "0.1.70"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "20b1438ef42c655665a8ab2c1c6d605a305f031d38d9be689ddfef41a20f3aa2"
+checksum = "80873f979f0a344a4ade87c2f70d9ccf5720b83b10c97ec7cd745895d021e85a"
 
 [[package]]
 name = "core_io"

src/libboard_artiq/src/drtioaux.rs

@@ -1,4 +1,5 @@
 use core::slice;
+use core::arch::asm;
 
 use core_io::{Error as IoError, ErrorKind as IoErrorKind};
 use crc;
@@ -39,6 +40,7 @@ pub fn copy_work_buffer(src: *mut u32, dst: *mut u32, len: isize) {
     // fix for artiq-zynq#344
     unsafe {
         for i in 0..(len / 4) {
+            asm!("", options(preserves_flags, nostack, readonly));
             *dst.offset(i) = *src.offset(i);
         }
     }

src/libboard_artiq/src/fiq.rs

@@ -1,6 +1,7 @@
 use libboard_zynq::{println, stdio};
 use libcortex_a9::{interrupt_handler, regs::MPIDR};
 use libregister::RegisterR;
+use core::arch::asm;
 
 #[cfg(has_si549)]
 use crate::si549;

src/libboard_artiq/src/lib.rs

@@ -1,7 +1,6 @@
 #![no_std]
 #![feature(never_type)]
 #![feature(naked_functions)]
-#![feature(asm)]
 
 extern crate core_io;
 extern crate crc;

src/libio/cursor.rs

@@ -62,12 +62,8 @@ impl Write for Cursor<&mut [u8]> {
     fn write(&mut self, buf: &[u8]) -> Result<usize, IoError> {
         let data = &mut self.inner[self.pos..];
         let len = buf.len().min(data.len());
-        for i in 0..len {
+        // as long as 'copy_work_buffer' is used in drtioaux, memcpy here is allowed
-            unsafe {
+        data[..len].copy_from_slice(&buf[..len]);
-                asm!("", options(preserves_flags, nostack, readonly));
-            }
-            data[i] = buf[i];
-        }
         self.pos += len;
         Ok(len)
     }

src/libio/lib.rs

@@ -1,6 +1,5 @@
 #![no_std]
 #![feature(never_type)]
-#![feature(asm)]
 
 #[cfg(feature = "alloc")]
 extern crate alloc;

src/libksupport/src/irq.rs

@@ -3,6 +3,7 @@ use core::sync::atomic::{AtomicBool, Ordering};
 use libboard_zynq::{gic, mpcore, println, stdio};
 use libcortex_a9::{asm, interrupt_handler, notify_spin_lock, regs::MPIDR, spin_lock_yield};
 use libregister::RegisterR;
+use core::arch::asm;
 
 extern "C" {
     static mut __stack1_start: u32;

src/libksupport/src/kernel/core1.rs

@@ -8,7 +8,7 @@ use dyld::{self, elf::EXIDX_Entry, Library};
 use libboard_zynq::{gic, mpcore};
 use libcortex_a9::{asm::{dsb, isb},
                    cache::{bpiall, dcci_slice, iciallu},
-                   enable_fpu, sync_channel};
+                   sync_channel};
 use libsupport_zynq::ram;
 use log::{debug, error, info};
 
@@ -126,7 +126,6 @@ impl KernelImage {
 
 #[no_mangle]
 pub extern "C" fn main_core1() {
-    enable_fpu();
     debug!("Core1 started");
 
     ram::init_alloc_core1();

src/libksupport/src/lib.rs

@@ -1,10 +1,8 @@
 #![no_std]
-#![allow(incomplete_features)]
 #![feature(c_variadic)]
 #![feature(const_btree_new)]
 #![feature(inline_const)]
 #![feature(naked_functions)]
-#![feature(asm)]
 
 #[macro_use]
 extern crate alloc;

src/runtime/src/main.rs

@@ -4,6 +4,7 @@
 #![feature(alloc_error_handler)]
 #![feature(const_btree_new)]
 #![feature(panic_info_message)]
+#![feature(lang_items)]
 
 #[macro_use]
 extern crate alloc;
@@ -43,6 +44,11 @@ extern "C" {
     static __exceptions_start: u32;
 }
 
+// linker may complain about missing rust_eh_personality but it is unused
+#[lang = "eh_personality"]
+#[allow(unused)]
+pub fn dummy_personality() { }
+
 #[cfg(all(feature = "target_kasli_soc", has_virtual_leds))]
 async fn io_expanders_service(
     i2c_bus: RefCell<&mut libboard_zynq::i2c::I2c>,

src/satman/src/main.rs

@@ -1,6 +1,6 @@
 #![no_std]
 #![no_main]
-#![feature(alloc_error_handler, never_type, panic_info_message)]
+#![feature(alloc_error_handler, never_type, panic_info_message, lang_items)]
 
 #[macro_use]
 extern crate log;
@@ -61,6 +61,11 @@ extern "C" {
     static __exceptions_start: u32;
 }
 
+// linker may complain about missing rust_eh_personality but it is unused
+#[lang = "eh_personality"]
+#[allow(unused)]
+pub fn dummy_personality() { }
+
 fn drtiosat_reset(reset: bool) {
     unsafe {
         csr::drtiosat::reset_write(if reset { 1 } else { 0 });