Compare commits

...

2 Commits

Author SHA1 Message Date
morgan a597d0b8e2 wrpll runtime: reduce mmcm output jitter
rtio_clocking: update mmcm setting to use HIGH bandwidth
2024-04-26 15:42:21 +08:00
morgan dcdad71909 SMAFreqMulti: set mmcm bw to HIGH for lower jitter 2024-04-26 15:01:06 +08:00
2 changed files with 8 additions and 8 deletions

View File

@ -203,7 +203,7 @@ class SMAFrequencyMultiplier(Module, AutoCSR):
# MMCME2 is capable to accept 10MHz input while PLLE2 only support down to 19MHz input (DS191) # MMCME2 is capable to accept 10MHz input while PLLE2 only support down to 19MHz input (DS191)
# The MMCME2 can be reconfiged during runtime using the Dynamic Reconfiguration Ports # The MMCME2 can be reconfiged during runtime using the Dynamic Reconfiguration Ports
Instance("MMCME2_ADV", Instance("MMCME2_ADV",
p_BANDWIDTH="LOW", # lower jitter p_BANDWIDTH="HIGH", # lower output jitter (see https://support.xilinx.com/s/question/0D52E00006iHqRqSAK)
o_LOCKED=self.mmcm_locked.status, o_LOCKED=self.mmcm_locked.status,
i_RST=self.mmcm_reset.storage, i_RST=self.mmcm_reset.storage,

View File

@ -278,8 +278,8 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
lock_reg2: 0x7c01, lock_reg2: 0x7c01,
lock_reg3: 0xffe9, lock_reg3: 0xffe9,
power_reg: 0x9900, power_reg: 0x9900,
filt_reg1: 0x0808, filt_reg1: 0x1008,
filt_reg2: 0x0800, filt_reg2: 0x8800,
}, },
false, false,
), ),
@ -295,8 +295,8 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
lock_reg2: 0x7c01, lock_reg2: 0x7c01,
lock_reg3: 0xffe9, lock_reg3: 0xffe9,
power_reg: 0x9900, power_reg: 0x9900,
filt_reg1: 0x0808, filt_reg1: 0x9908,
filt_reg2: 0x9800, filt_reg2: 0x8100,
}, },
false, false,
), ),
@ -312,8 +312,8 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
lock_reg2: 0x7c01, lock_reg2: 0x7c01,
lock_reg3: 0xffe9, lock_reg3: 0xffe9,
power_reg: 0x9900, power_reg: 0x9900,
filt_reg1: 0x0808, filt_reg1: 0x9108,
filt_reg2: 0x9800, filt_reg2: 0x0100,
}, },
false, false,
), ),
@ -329,7 +329,7 @@ fn wrpll_setup(timer: &mut GlobalTimer, clk: RtioClock, si549_settings: &si549::
lock_reg2: 0x7001, lock_reg2: 0x7001,
lock_reg3: 0xf3e9, lock_reg3: 0xf3e9,
power_reg: 0x0100, power_reg: 0x0100,
filt_reg1: 0x0808, filt_reg1: 0x9908,
filt_reg2: 0x1100, filt_reg2: 0x1100,
}, },
true, true,