kasli_soc: enable clock buffer after system clock domain reset

src/runtime/src/rtio_clocking.rs

@@ -84,6 +84,7 @@ fn init_rtio(timer: &mut GlobalTimer) {
         panic!("SYS CLK did not switch");
     }
     unsafe {
+        pl::csr::sys_crg::clock_switch_write(1); //re-enable clock input buffer after system clock domain reset
         pl::csr::rtio_core::reset_phy_write(1);
     }
     info!("SYS PLL locked");
@@ -103,6 +104,7 @@ fn init_drtio(timer: &mut GlobalTimer) {
         panic!("SYS CLK did not switch");
     }
     unsafe {
+        pl::csr::drtio_transceiver::stable_clkin_write(1); //re-enable clock input buffer after system clock domain reset
         pl::csr::rtio_core::reset_phy_write(1);
         pl::csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
     }

src/satman/src/main.rs

@@ -642,6 +642,7 @@ pub extern "C" fn main_core0() -> i32 {
     }
 
     unsafe {
+        csr::drtio_transceiver::stable_clkin_write(1); //re-enable clock input buffer after system clock domain reset
         csr::drtio_transceiver::txenable_write(0xffffffffu32 as _);
     }