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1 Commits
f56959aed7
...
9b76896edd
Author | SHA1 | Date |
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Egor Savkin | 9b76896edd |
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@ -114,7 +114,7 @@ class SMAClkinForward(Module):
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class GenericStandalone(SoCCore):
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class GenericStandalone(SoCCore):
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def __init__(self, description, acpki=False):
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def __init__(self, description, acpki=False):
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self.acpki = acpki
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self.acpki = acpki
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rtio_clk_freq = description["rtio_frequency"]
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sys_clk_freq = 125e6
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platform = kasli_soc.Platform()
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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platform.toolchain.bitstream_commands.extend([
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@ -143,7 +143,7 @@ class GenericStandalone(SoCCore):
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self.ps7.cd_sys.clk,
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self.ps7.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.rtio_crg.cd_rtio.clk)
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fix_serdes_timing_path(platform)
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fix_serdes_timing_path(platform)
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self.config["CLOCK_FREQUENCY"] = int(rtio_clk_freq)
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self.config["CLOCK_FREQUENCY"] = int(sys_clk_freq)
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self.rtio_channels = []
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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@ -228,7 +228,7 @@ class GenericMaster(SoCCore):
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pads=data_pads,
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pads=data_pads,
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sys_clk_freq=sys_clk_freq)
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sys_clk_freq=sys_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.csr_devices.append("drtio_transceiver")
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self.config["CLOCK_FREQUENCY"] = int(rtio_clk_freq)
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self.config["CLOCK_FREQUENCY"] = int(sys_clk_freq)
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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@ -461,7 +461,7 @@ class GenericSatellite(SoCCore):
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rtio_clk_period = 1e9/rtio_clk_freq
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rtio_clk_period = 1e9/rtio_clk_freq
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.config["CLOCK_FREQUENCY"] = int(rtio_clk_freq)
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self.config["CLOCK_FREQUENCY"] = int(sys_clk_freq)
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self.submodules.siphaser = SiPhaser7Series(
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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si5324_clkin=platform.request("cdr_clk"),
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